Search results for "G. Edward Suh"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Daniel Lo, Greg Malysa, G. Edward Suh	FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric.	FPL	2011	DBLP DOI BibTeX RDF
1	Wing-Kei S. Yu, Ruirui C. Huang, Sarah Q. Xu, Sung-En Wang, Edwin Kan, G. Edward Suh	SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading.	ISCA	2011	DBLP DOI BibTeX RDF
1	Nithin Michael, Milen Nikolov, Ao Tang, G. Edward Suh, Christopher Batten	Analysis of application-aware on-chip routing under traffic uncertainty.	NOCS	2011	DBLP BibTeX RDF
1	Daniel Y. Deng, G. Edward Suh	Precise exception support for decoupled run-time monitoring architectures.	ICCD	2011	DBLP DOI BibTeX RDF
1	Pravin Prabhu, Ameen Akel, Laura M. Grupp, Wing-Kei S. Yu, G. Edward Suh, Edwin Kan, Steven Swanson	Extracting Device Fingerprints from Flash Memory by Exploiting Physical Variations.	TRUST	2011	DBLP DOI BibTeX RDF
1	Ruirui C. Huang, David Grawrock, David C. Doughty, G. Edward Suh	Systematic Security Assessment at an Early Processor Design Stage.	TRUST	2011	DBLP DOI BibTeX RDF
1	Ruirui C. Huang, G. Edward Suh	IVEC: off-chip memory integrity protection for both security and reliability.	ISCA	2010	DBLP DOI BibTeX RDF	security, fault tolerance, reliability, error detection, error correction, memory systems
1	Ruirui C. Huang, Daniel Y. Deng, G. Edward Suh	Orthrus: efficient software integrity protection on multi-cores.	ASPLOS	2010	DBLP DOI BibTeX RDF	replication-aware architecture, software diversity and redundancy, software security, multi-core architecture, memory protection
1	Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh	Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric.	MICRO	2010	DBLP DOI BibTeX RDF
1	Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh	Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dynamic inspection, reconfigurable microprocessors, fpga
1	Shantanu Rajwade, Wing-Kei S. Yu, Sarah Q. Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan	Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash.	SoCC	2010	DBLP DOI BibTeX RDF
1	Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edward Suh, Marten van Dijk, Srinivas Devadas	Application-aware deadlock-free oblivious routing.	ISCA	2009	DBLP DOI BibTeX RDF	systems-on-chip, oblivious routing, on-chip interconnection networks
1	Keun Sup Shim, Myong Hyon Cho, Michel A. Kinsy, Tina Wen, Mieszko Lis, G. Edward Suh, Srinivas Devadas	Static virtual channel allocation in oblivious routing.	NOCS	2009	DBLP DOI BibTeX RDF
1	Daniel Y. Deng, Andrew H. Chan, G. Edward Suh	Hardware authentication leveraging performance limits in detailed simulations and emulations.	DAC	2009	DBLP DOI BibTeX RDF	hardware authentication, secure processors
1	Myong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas	Diastolic arrays: throughput-driven reconfigurable computing.	ICCAD	2008	DBLP DOI BibTeX RDF
1	G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas	Aegis: A Single-Chip Secure Processor.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	Aegis, FPGA, architecture, secure processor, single chip
1	G. Edward Suh, Srinivas Devadas	Physical Unclonable Functions for Device Authentication and Secret Key Generation.	DAC	2007	DBLP DOI BibTeX RDF
1	Marten van Dijk, Dwaine E. Clarke, Blaise Gassend, G. Edward Suh, Srinivas Devadas	Speeding up Exponentiation using an Untrusted Computational Resource.	Des. Codes Cryptography	2006	DBLP DOI BibTeX RDF	AMS Classification 94A60
1	Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh, Marten van Dijk, Srinivas Devadas	Extracting secret keys from integrated circuits.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Dwaine E. Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten van Dijk, Srinivas Devadas	Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data.	IEEE Symposium on Security and Privacy	2005	DBLP DOI BibTeX RDF
1	G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas	Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions.	ISCA	2005	DBLP DOI BibTeX RDF
1	G. Edward Suh, Larry Rudolph, Srinivas Devadas	Dynamic Partitioning of Shared Cache Memory.	The Journal of Supercomputing	2004	DBLP DOI BibTeX RDF	CMP and SMT, shared caches, cache partitioning
1	G. Edward Suh, Jae W. Lee, David Zhang, Srinivas Devadas	Secure program execution via dynamic information flow tracking.	ASPLOS	2004	DBLP DOI BibTeX RDF	format string, hardware tagging, buffer overflow
1	G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas	Efficient Memory Integrity Verification and Encryption for Secure Processors.	MICRO	2003	DBLP DOI BibTeX RDF
1	Prabhat Jain, G. Edward Suh, Srinivas Devadas	Embedded intelligent SRAM.	DAC	2003	DBLP DOI BibTeX RDF	computation partitioning, embedded, SRAM, intelligent
1	G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas	AEGIS: architecture for tamper-evident and tamper-resistant processing.	ICS	2003	DBLP DOI BibTeX RDF	software licensing, secure processors, certified execution
1	Dwaine E. Clarke, Srinivas Devadas, Marten van Dijk, Blaise Gassend, G. Edward Suh	Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking.	ASIACRYPT	2003	DBLP DOI BibTeX RDF
1	Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas	Caches and Hash Trees for Efficient Memory Integrity Verification.	HPCA	2003	DBLP DOI BibTeX RDF
1	G. Edward Suh, Srinivas Devadas, Larry Rudolph	A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning.	HPCA	2002	DBLP DOI BibTeX RDF
1	G. Edward Suh, Srinivas Devadas, Larry Rudolph	Analytical cache models with applications to cache partitioning.	ICS	2001	DBLP DOI BibTeX RDF
1	G. Edward Suh, Larry Rudolph, Srinivas Devadas	Effects of Memory Performance on Parallel Job Scheduling.	JSSPP	2001	DBLP DOI BibTeX RDF

Publications of "G. Edward Suh" ( http://dblp.L3S.de/Authors/G._Edward_Suh )