Search results for "G. Venkatesh"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	G. Venkatesh	Temporal Logic with Preferences and Reasoning About Games.	Proof, Computation and Agency	2011	DBLP DOI BibTeX RDF
1	A. P. Sarath Chandar, S. Arun Balaji, G. Venkatesh, Susan Elias	CDPN: Communicating Dynamic Petri Net for Adaptive Multimedia Presentation.	ICT	2010	DBLP DOI BibTeX RDF
1	G. Venkatesh	Reasoning About Game Equilibria Using Temporal Logic.	FSTTCS	2004	DBLP DOI BibTeX RDF
1	Manoranjan Satpathy, Amitabha Sanyal, G. Venkatesh	Improved Register Usage for Functional Programs through Multiple Function Versions.	Journal of Functional and Logic Programming	1998	DBLP BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Low-power realization of FIR filters on programmable DSPs.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.	VLSI Design	1998	DBLP DOI BibTeX RDF	Hardware/Software High Level Synthesis, Low Power Design, FIR Filters
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Extensions to Programmable DSP architectures for Reduced Power Dissipation.	VLSI Design	1998	DBLP DOI BibTeX RDF	Low Power Design, DSP Architecture
1	Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh	Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters.	VLSI Design	1998	DBLP DOI BibTeX RDF	High Level Synthesis-Transformations, FIR Filters
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	Mohsin Ahmed, G. Venkatesh	Dense Time Logic Programming.	J. Symb. Comput.	1996	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar	Monitoring machine based synthesis technique for concurrent error detection in finite state machines.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	monitoring machines, finite state machine synthesis, concurrent error detection
1	Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar	Optimized Code Generation of Multiplication-free Linear Transforms.	DAC	1996	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Low power realization of FIR filters using multirate architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips
1	Milind Gandhe, G. Venkatesh, Amitabha Sanyal	Correcting Errors in the Curry System.	FSTTCS	1996	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar	Concurrent Error Detection Using Monitoring Machines.	IEEE Design & Test of Computers	1995	DBLP DOI BibTeX RDF
1	Milind Gandhe, G. Venkatesh, Amitabha Sanyal	Labeled Lambda-Calculus and a Generalized Notion of Strictness (An Extended Abstract).	ASIAN	1995	DBLP DOI BibTeX RDF
1	Manoranjan Satpathy, Amitabha Sanyal, G. Venkatesh	An Automaton-Driven Frame Disposal Algorithm and its Proof of Correctness.	ASIAN	1995	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Techniques for low power realization for FIR filters.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh	A new methodology for the design of low-cost fail safe circuits and networks.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-cost fail safe circuits, safety critical electronic systems, input-output encoding problems, output encoding technique, low-cost design, systematic framework, graph theory, design methodology, encoding, combinational circuits, combinational circuits, graph embedding, graceful degradation, logic partitioning
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Synthesis of multiplier-less FIR filters with minimum number of additions.	ICCAD	1995	DBLP DOI BibTeX RDF	MCM based structures, iterative elimination, low pass FIR filters, circuit CAD, FIR filters, network synthesis, optimizing transformations, binary representations
1	Mohsin Ahmed, G. Venkatesh	A Propositional Dense Time Logic (Based on Nested Sequences).	TAPSOFT	1993	DBLP DOI BibTeX RDF	ordinal trees, Temporal logic, dense time
1	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar	State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits.	VLSI Design	1993	DBLP BibTeX RDF
1	Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran	A Behavioral Fault Simulator for Ideal.	IEEE Design & Test of Computers	1992	DBLP DOI BibTeX RDF
1	Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh	A methodology for the design of SFS/SCD circuits for a class of unordered codes.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	strongly fault-secure, strongly code disjoint, concurrent error detection, Self-checking circuits, unordered codes
1	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar	A Methodology for Designing Optimal Self-Checking Sequential Circuits.	ITC	1991	DBLP DOI BibTeX RDF
1	Milind Gandhe, G. Venkatesh	Improving Prolog Performance by Inductive Proof Generalizations.	KBCS	1989	DBLP DOI BibTeX RDF
1	S. Bapat, G. Venkatesh	Reasoning about digital systems using temporal logic.	DAC	1986	DBLP DOI BibTeX RDF
1	G. Venkatesh	A Decision Method for Temporal Logic Based on Resolution.	FSTTCS	1985	DBLP DOI BibTeX RDF
1	Donald F. Towsley, G. Venkatesh	Window Random Access Protocols for Local Computer Networks.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF

Publications of "G. Venkatesh" ( http://dblp.L3S.de/Authors/G._Venkatesh )