Search results for "GALs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet	Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.	NOCS	2008	DBLP DOI BibTeX RDF	Pausable clock, Vdd Hopping, Network-on-Chip, power, DVFS, GALS
3	Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang	A GALS Infrastructure for a Massively Parallel Multiprocessor.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	massively parallel multiprocessor, Spinnaker, self-timed interconnect, GALS, neural modeling
3	Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux	A Survey and Taxonomy of GALS Design Styles.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	globally asynchronous, locally synchronous (GALS), clock domains, pausible clocks, loosely synchronous, synchronization, asynchronous
3	Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley	GALS SoC interconnect bus for wireless sensor network processor platforms.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	SoC bus, application specific bus, system on chip bus, WSN, wireless sensor network, low power, GALS
3	Supratik Chakraborty, Joycee Mekie, Dinesh K. Sharma	Reasoning about synchronization in GALS systems.	Formal Methods in System Design	2006	DBLP DOI BibTeX RDF	Symbolic timing analysis, GALS systems, Multi-clocked systems, Symbolic delay constraints, Synchronization constraints, Sequencing constraints
3	Grigorios Magklis, Pedro Chaparro, José González, Antonio González	Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture.	ISLPED	2006	DBLP DOI BibTeX RDF	MCD, energy efficiency, DVS, microarchitecture, GALS
3	Matthew W. Heath, Wayne P. Burleson, Ian G. Harris	Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	test, debug, SoC, nondeterminism, GALS, globally asynchronous locally synchronous
2	Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres	A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	cryptography attacks, DPA, asynchronous, SCA, GALS, design and test, DEMA
2	Jean-Michel Chabloz, Ahmed Hemani	Distributed DVFS using rationally-related frequencies and discrete voltage levels.	ISLPED	2010	DBLP DOI BibTeX RDF	GRLS, DVFS, GALS
2	Hubert Garavel, Damien Thivolle	Verification of GALS Systems by Combining Synchronous Languages and Process Calculi.	SPIN	2009	DBLP DOI BibTeX RDF
2	Nicolas Coste, Holger Hermanns, Etienne Lantreibecq, Wendelin Serwe	Towards Performance Prediction of Compositional Models in Industrial GALS Designs.	CAV	2009	DBLP DOI BibTeX RDF
2	Avinash Malik, Zoran A. Salcic, Alain Girault, Adam Walker, Sung Chul Lee	A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution.	JTRES	2009	DBLP DOI BibTeX RDF	synchronous and asynchronous concurrency, multiprocessor, GALS, reactivity
2	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla	A Trace-Based Framework for Verifiable GALS Composition of IPs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades	Multisynchronous and Fully Asynchronous NoCs for GALS Architectures.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
2	Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz	Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures.	DDECS	2008	DBLP DOI BibTeX RDF
2	Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas	Architecture and Evaluation of an Asynchronous Array of Simple Processors.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
2	Michael Kishinevsky, Sandeep K. Shukla, Ken S. Stevens	Guest Editors' Introduction: GALS Design and Validation.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	design, synchronous, validation, asynchronous
2	Ümit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu	Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip.	DAC	2007	DBLP DOI BibTeX RDF
2	Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya	Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.	DATE	2007	DBLP DOI BibTeX RDF
2	Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani	GALS Based Shared Test Architecture for Embedded Memories.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet	Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	asynchronous/synchronous operation, VLSI, interfaces, GALS
2	Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A. Lee, Dong-Soo Har	Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	multiple outstanding transactions, in-order/out-of-order transaction completion, asynchronous on-chip bus, GALS
2	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou	High Rate Data Synchronization in GALS SoCs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Sandeep K. Shukla, Michael Theobald	Special issue on formal methods for globally asynchronous and locally synchronous (GALS) systems.	Formal Methods in System Design	2006	DBLP DOI BibTeX RDF
2	Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen	Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA.	FPL	2006	DBLP DOI BibTeX RDF
2	Abbas Sheibanyrad, Alain Greiner	Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures.	PATMOS	2006	DBLP DOI BibTeX RDF
2	YongKang Zhu, David H. Albonesi	Synergistic temperature and energy management in GALS processor architectures.	ISLPED	2006	DBLP DOI BibTeX RDF	dynamic temperature management (DTM), dynamic voltage scaling (DVS)
2	Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen	Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA.	DSD	2006	DBLP DOI BibTeX RDF
2	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan	Interface Design for Rationally Clocked GALS Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
2	Edith Beigné, Pascal Vivet	Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
2	Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner	GALS at ETH Zurich: Success or Failure.	ASYNC	2006	DBLP DOI BibTeX RDF
2	Xin Jia, Ranga Vemuri	Studying a GALS FPGA architecture using a parameterized automatic design flow.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Tomi Westerlund, Juha Plosila	Time Aware Modelling and Analysis of Multiclocked VLSI Systems.	ICFEM	2006	DBLP DOI BibTeX RDF	Timed Action Systems, formal methods, time, GALS
2	Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli	A Framework for Modeling the Distributed Deployment of Synchronous Designs.	Formal Methods in System Design	2006	DBLP DOI BibTeX RDF	Distributed systems, GALS, Desynchronization, Latency-insensitive design
2	Dumitru Potop-Butucaru, Benoît Caillaud, Albert Benveniste	Concurrency in Synchronous Systems.	Formal Methods in System Design	2006	DBLP DOI BibTeX RDF	Globally asynchronous locally synchronous (GALS), Concurrency, Synchronous, Distribution, Desynchronization, Trace theory
2	Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy	GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Asynchronous/synchronous operations, fault tolerance, energy-aware systems, algorithms implemented in hardware
2	Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy	A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.	ISQED	2005	DBLP DOI BibTeX RDF
2	Eckhard Grass, Frank Winkler, Milos Krstic, Alexandra Julius, Christian Stahl, Maxim Piz	Enhanced GALS Techniques for Datapath Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Dynamic Instruction Cascading on GALS Microprocessors.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Christian Stahl, Wolfgang Reisig, Milos Krstic	Hazard Detection in a GALS Wrapper: A Case Study.	ACSD	2005	DBLP DOI BibTeX RDF
2	Milos Krstic, Eckhard Grass	BIST Technique for GALS Systems.	DSD	2005	DBLP DOI BibTeX RDF
2	Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
2	Milos Krstic, Eckhard Grass, Christian Stahl	Request-Driven GALS Technique for Wireless Communication System.	ASYNC	2005	DBLP DOI BibTeX RDF
2	Xin Jia, Ranga Vemuri	Using GALS architecture to reduce the impact of long wire delay on FPGA performance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Diana Marculescu, Emil Talpes	Variability and energy awareness: a microarchitecture-level perspective.	DAC	2005	DBLP DOI BibTeX RDF	GALS design, power consumption, variability
2	Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A. Lee, Dong-Soo Har	High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	asynchronous on-chip bus, in-order completion, multiple issue, out-of-order completion, SoC, GALS
2	Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi	A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	on-chip clock generation, FPGA, GALS
2	Sonia López, Oscar Garnica, José Manuel Colmenar	Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner	A switch architecture and signal synchronization for GALS system-on-chips.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC switch, clock stretching, synchronization, GALS
2	Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas	Hiding Synchronization Delays in a GALS Processor Microarchitecture.	ASYNC	2004	DBLP DOI BibTeX RDF
2	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou	Data Synchronization Issues in GALS SoCs.	ASYNC	2004	DBLP DOI BibTeX RDF
2	Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott	Dynamically Trading Frequency for Complexity in a GALS Microprocessor.	MICRO	2004	DBLP DOI BibTeX RDF
2	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma	Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	S. Ramesh, Sampada Sonalkar, Vijay D'Silva, Naveen Chandra, B. Vijayalakshmi	A Toolset for Modelling and Verification of GALS Systems.	CAV	2004	DBLP DOI BibTeX RDF
2	Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili	Optimal partitioning of globally asychronous locally synchronous processor arrays.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	VLSI, partitioning, power optimization, GALS
2	Milos Krstic, Eckhard Grass	New GALS Technique for Datapath Architectures.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Venkata Syam P. Rapaka, Diana Marculescu	A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores.	ISLPED	2003	DBLP DOI BibTeX RDF	issue window design, mixed-clock circuits, GALS
2	George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson	Point to Point GALS Interconnect.	ASYNC	2002	DBLP DOI BibTeX RDF
2	Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters, Paul Wielage	Clock Synchronization through Handshake Signalling.	ASYNC	2002	DBLP DOI BibTeX RDF	GALS systems, pausible clocks, asynchronous crossbar/bus, processor/memory architectures
2	Alain Girault, Clément Ménier	Automatic Production of Globally Asynchronous Locally Synchronous Systems.	EMSOFT	2002	DBLP DOI BibTeX RDF	Globally synchronous-locally asynchronous (GALS), asynchronous communications, hardware/software codesign, distributed architectures, synchronous circuits, automatic distribution
1	Hala A. Farouk, Mahmoud T. El-Hadidi, Ahmed A. El-Farag	GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors.	IJNC	2012	DBLP BibTeX RDF
1	Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang	Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato	On the Impact of Within-Die Process Variation in GALS-Based NoC Performance.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Filipe Moutinho, Luís Gomes	Asynchronous-Channels and Time-Domains Extending Petri Nets for GALS Systems.	DoCEIS	2012	DBLP DOI BibTeX RDF
1	Muhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic	JOP-plus - A processor for efficient execution of java programs extended with GALS concurrency.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jean-Michel Chabloz, Ahmed Hemani	Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Xin Fan, Milos Krstic, Eckhard Grass, Birgit Sanders, Christoph Heer	Exploring pausible clocking based GALS design for 40-nm system integration.	DATE	2012	DBLP BibTeX RDF
1	Dongkun Shin, Woojoong Kim, Soontae Kwon, Tae Hee Han	Communication-aware VFI partitioning for GALS-based networks-on-chip.	Design Autom. for Emb. Sys.	2011	DBLP DOI BibTeX RDF
1	Alessandro Strano, Carles Hernández, Federico Silla, Davide Bertozzi	Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design.	IJERTCS	2011	DBLP DOI BibTeX RDF
1	Abbas Rahimi, Mostafa E. Salehi, Siamak Mohammadi, Sied Mehdi Fakhraie	Low-energy GALS NoC with FIFO - Monitoring dynamic voltage scaling.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Wei-Tsun Sun, Zoran Salcic	GALS-Designer: A design framework for GALS software systems.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Luis A. Plana, David M. Clark, Simon Davidson, Steve Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge	SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.	JETC	2011	DBLP DOI BibTeX RDF
1	Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin	A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Muhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic	GALS-JOP: A Java Embedded Processor for GALS Reactive Programs.	DASC	2011	DBLP DOI BibTeX RDF
1	Avinash Malik, Alain Girault, Zoran Salcic	A GALS Language for Dynamic Distributed and Reactive Programs.	ACSD	2011	DBLP DOI BibTeX RDF
1	Hala A. Farouk, Mahmoud T. El-Hadidi, Ahmed A. El Farag	GALS-Based LPSP: Implementation of a Novel Architecture for Low Power High Performance Security Processors.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Xin Fan, Milos Krstic, Christoph Wolf, Eckhard Grass	GALS Design for On-chip Ground Bounce Suppression.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Zhiyi Yu, Zewen Shi, Xiaoyang Zeng	Fault tolerant computing for stream DSP applications using GALS multi-core processors.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Jean-Michel Chabloz, Ahmed Hemani	A GALS Network-on-Chip based on rationally-related frequencies.	ICCD	2011	DBLP DOI BibTeX RDF
1	Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas	A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Zhiyi Yu, Bevan M. Baas	A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad	Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Avinash Malik, Zoran Salcic, Partha S. Roop, Alain Girault	SystemJ: A GALS language for system level design.	Computer Languages, Systems & Structures	2010	DBLP DOI BibTeX RDF
1	Mohammad Fattah, Abdurrahman Manian, Abbas Rahimi, Siamak Mohammadi	A High Throughput Low Power FIFO Used for GALS NoC Buffers.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres	A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato	Improving the Performance of GALS-Based NoCs in the Presence of Process Variation.	NOCS	2010	DBLP DOI BibTeX RDF
1	Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin	A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors.	NOCS	2010	DBLP DOI BibTeX RDF
1	Tim Kranich, Mladen Berekovic	NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems.	DSD	2010	DBLP DOI BibTeX RDF
1	Xin Fan, Milos Krstic, Christoph Wolf, Eckhard Grass	A GALS FFT processor with clock modulation for low-EMI applications.	ASAP	2010	DBLP DOI BibTeX RDF
1	Wei-Tsun Sun, Zoran Salcic, Avinash Malik	LibGALS: a library for GALS systems design and modeling.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi	Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.	DATE	2010	DBLP BibTeX RDF
1	Yvain Thonnart, Pascal Vivet, Fabien Clermidy	A fully-asynchronous low-power framework for GALS NoC integration.	DATE	2010	DBLP BibTeX RDF
1	Duan Wei, Fan Qi Fei, Huang Kun, Zhang Ge	VB-DVFS: A new algorithm for power efficiency of CMP with GALS.	ICECS	2010	DBLP DOI BibTeX RDF
1	Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira, Isabel C. Teixeira, J. C. Silva, Pedro Lousã, João Varela	Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems.	DDECS	2010	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
1	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das	Coordinated power management of voltage islands in CMPs.	SIGMETRICS	2010	DBLP DOI BibTeX RDF	chip multiprocessors (CMP), control theory, GALs, DVFs
1	Daniel Gebhardt, JunBok You, Kenneth S. Stevens	Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs.	NOCS	2010	DBLP DOI BibTeX RDF	network, CAD, SoC, topology, asynchronous, floorplan, router, EDA, NoC, GALS
1	Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi	Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs.	NOCS	2010	DBLP DOI BibTeX RDF	asynchronous interconnect, NoC, GALS, on-chip networks
1	Mohammad Reza Kakoee, Igor Loi, Luca Benini	A new physical routing approach for robust bundled signaling on NoC links.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	NoC global link routing, bundled routing, delay matching, pin placement, robust signaling, wire length variability, bus routing
1	René Gagné, Jean Belzile, Claude Thibeault	From synchronous to GALS: A new architecture for FPGAs.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF