Search results for "Gabriel H. Loh"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim	3D-MAPS: 3D Massively parallel processor with stacked memory.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Andrew Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger	Preventing PCM banks from seizing too much power.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	A register-file approach for row buffer caches in die-stacked DRAMs.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Mark D. Hill	Efficiently enabling conventional block sizes for very large die-stacked DRAM caches.	MICRO	2011	DBLP DOI BibTeX RDF
1	Yuejian Xie, Gabriel H. Loh	Thread-aware dynamic shared cache compression in multi-core processors.	ICCD	2011	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Yuan Xie	3D Stacked Microprocessor: Are We There Yet?	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger	Use ECP, not ECC, for hard failures in resistive memories.	ISCA	2010	DBLP DOI BibTeX RDF	hard failures, resistive memories, memory, error correction, phase change memory
1	Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammed M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim	Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.	CICC	2010	DBLP DOI BibTeX RDF
1	Yuejian Xie, Gabriel H. Loh	Scalable Shared-Cache Management by Containing Thrashing Workloads.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Gabriel H. Loh	Design and optimization of the store vectors memory dependence predictor.	TACO	2009	DBLP DOI BibTeX RDF
1	Kiran Puttaswamy, Gabriel H. Loh	3D-Integrated SRAM Components for High-Performance Microprocessors.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Yuejian Xie, Gabriel H. Loh	PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches.	ISCA	2009	DBLP DOI BibTeX RDF	cache, multi-core, sharing, contention, insertion, promotion
1	Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie	Zesto: A cycle-level simulator for highly detailed microarchitecture exploration.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.	MICRO	2009	DBLP DOI BibTeX RDF
1	Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim	Thermal optimization in multi-granularity multi-core floorplanning.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Anne Bracy, Hong Wang 0003, Gabriel H. Loh	Criticality-based optimizations for efficient load processing.	HPCA	2009	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Daniel A. Jiménez	Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Computer architecture, Branch prediction
1	Gabriel H. Loh	3D-Stacked Memory Architectures for Multi-core Processors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	A modular 3d processor for flexible product design and technology migration.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	modular, superscalar, 3d-integration
1	Mauricio Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeff Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu	A Segmented Bloom Filter Algorithm for Efficient Predictors.	SBAC-PAD	2008	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Milos Prvulovic, Gabriel H. Loh	PEEP: Exploiting predictability of memory dependences in SMT processors.	HPCA	2008	DBLP DOI BibTeX RDF
1	Peter G. Sassone, D. Scott Wills, Gabriel H. Loh	Static strands: Safely exposing dependence chains for increasing embedded power efficiency.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	dependency collapsing, Architecture, energy, sequentiality
1	Gabriel H. Loh, Yuan Xie, Bryan Black	Processor Design in 3D Die-Stacking Technologies.	IEEE Micro	2007	DBLP DOI BibTeX RDF	processor architectures, computer systems organization, 3D integration
1	Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh	Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black	Matrix scheduler reloaded.	ISCA	2007	DBLP DOI BibTeX RDF	picker, scheduler, microarchitecture, matrix, wakeup
1	Kiran Puttaswamy, Gabriel H. Loh	Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors.	DAC	2007	DBLP DOI BibTeX RDF
1	Kiran Puttaswamy, Gabriel H. Loh	Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors.	HPCA	2007	DBLP DOI BibTeX RDF
1	Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein	Design space exploration for 3D architectures.	JETC	2006	DBLP DOI BibTeX RDF	hardware, microarchitecture, processor architectures, 3D integration
1	Kiran Puttaswamy, Gabriel H. Loh	Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	Revisiting the performance impact of branch predictor latencies.	ISPASS	2006	DBLP DOI BibTeX RDF
1	Kiran Puttaswamy, Gabriel H. Loh	Dynamic instruction schedulers in a 3-dimensional integration technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	3D technology, instruction scheduler
1	Kiran Puttaswamy, Gabriel H. Loh	Thermal analysis of a 3D die-stacked high-performance microprocessor.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	3D technology, thermals, power density
1	Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Pat Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb	Die Stacking (3D) Microarchitecture.	MICRO	2006	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Gabriel H. Loh	Fire-and-Forget: Load/Store Scheduling with No Store Queue at All.	MICRO	2006	DBLP DOI BibTeX RDF
1	Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh	Adaptive Caches: Effective Shaping of Cache Behavior to Workloads.	MICRO	2006	DBLP DOI BibTeX RDF
1	Chinnakrishnan S. Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee	Entropy-based low power data TLB design.	CASES	2006	DBLP DOI BibTeX RDF	low-power TLB, spatial and temporal locality, entropy
1	Daniel A. Jiménez, Gabriel H. Loh	Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
1	Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh	Microarchitectural floorplanning under performance and thermal tradeoff.	DATE	2006	DBLP DOI BibTeX RDF
1	Kiran Puttaswamy, Gabriel H. Loh	The impact of 3-dimensional integration on the design of arithmetic units.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Gabriel H. Loh	Store vectors for scalable memory dependence prediction and scheduling.	HPCA	2006	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	Simulation Differences Between Academia and Industry: A Branch Prediction Case Study.	ISPASS	2005	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Kiran Puttaswamy, Gabriel H. Loh	Implementing Caches in a 3D Technology for High Performance Processors.	ICCD	2005	DBLP DOI BibTeX RDF
1	Peter G. Sassone, D. Scott Wills, Gabriel H. Loh	Static strands: safely collapsing dependence chains for increasing embedded power efficiency.	LCTES	2005	DBLP DOI BibTeX RDF	dependency collapsing, architecture, embedded, energy, sequentiality
1	Gabriel H. Loh, Dana S. Henry, Arvind Krishnamurthy	Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors.	J. Instruction-Level Parallelism	2003	DBLP BibTeX RDF
1	Gabriel H. Loh	Width-Partitioned Load Value Predictors.	J. Instruction-Level Parallelism	2003	DBLP BibTeX RDF
1	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Asymptotically Scalable Superscalar Processors.	Theory Comput. Syst.	2002	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Dana S. Henry	Predicting Conditional Branches With Fusion-Based Hybrid Predictors.	IEEE PACT	2002	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	Exploiting data-width locality to increase superscalar execution bandwidth.	MICRO	2002	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Dana S. Henry	Applying Machine Learning for Ensemble Branch Predictors.	IEA/AIE	2002	DBLP DOI BibTeX RDF
1	Dana S. Henry, Gabriel H. Loh, Rahul Sami	Speculative Clustered Caches for Clustered Processors.	ISHPC	2002	DBLP BibTeX RDF
1	Gabriel H. Loh	A time-stamping algorithm for efficient performance estimation of superscalar processors.	SIGMETRICS/Performance	2001	DBLP DOI BibTeX RDF
1	Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami	Circuits for wide-window superscalar processors.	ISCA	2000	DBLP DOI BibTeX RDF
1	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Scalable Superscalar Processors.	SPAA	1999	DBLP DOI BibTeX RDF

Publications of "Gabriel H. Loh" ( http://dblp.L3S.de/Authors/Gabriel_H._Loh )