| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Elio Consoli, Gaetano Palumbo, Melita Pennisi |
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo |
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits. |
IEEE Trans. on Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey |
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. |
ISSCC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Optimized design of parallel carry-select adders. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo |
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model. |
ECCTD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo |
An ultra-compact MOS model in nanometer technologies. |
ECCTD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, Melita Pennisi, Ramón González Carvajal |
Figures of merit for class AB input stages. |
ECCTD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Elio Consoli, Gaetano Palumbo, Melita Pennisi |
TG Master-Slave FFs: High-speed optimization. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo |
Verilog-A modeling of SPAD statistical phenomena. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
DET FF topologies: A detailed investigation in the energy-delay-area domain. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications. |
Journal of Circuits, Systems, and Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. |
PATMOS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers. |
Journal of Circuits, Systems, and Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Analysis and Modeling of Energy Consumption in RLC Tree Circuits. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
Step-response Optimization Techniques for Low-power Three-stage Operational Amplifiers for Large Capacitive Load Applications. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
A New Advanced RNMC Technique with Dual-active Current and Voltage Buffers for Low-power High-load Three-stage Amplifiers. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Elio Consoli, Gaetano Palumbo |
Optimum clock slope for flip-flops within a clock domain: Analysis and a case study. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Davide Marano, Gaetano Palumbo, Salvatore Pennisi |
A high-speed low-power output buffer amplifier for large-size LCD applications. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi |
Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Analysis of the impact of random process variations in CMOS tapered buffers. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosario Mita, Gaetano Palumbo |
High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes. |
IEEE T. Instrumentation and Measurement |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Power-Aware Design of Nanometer MCML Tapered Buffers. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi |
Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi |
Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi |
Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, Melita Pennisi |
AMOLED pixel driver circuits based on poly-Si TFTs: A comparison. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale |
Low-voltage LDO Compensation Strategy based on Current Amplifiers. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Power-delay optimization in MCML tapered buffers. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Massimo Poli, Gaetano Palumbo |
Explicit energy evaluation in RLC tree circuits with ramp inputs. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo |
Mixed Full Adder topologies for high-performance low-power arithmetic circuits. |
Microelectronics Journal |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Walter Aloisi, Giuseppe Di Cataldo, Gaetano Palumbo, Salvatore Pennisi |
Miller Compensation: Optimization with Current Buffer/Amplifier. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Falconi, Arnaldo D'Amico, Gianluca Giustolisi, Gaetano Palumbo |
Rosenstark-like Representation of Feedback Amplifier Resistance. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosario Mita, Gaetano Palumbo, Pier Giorgio Fallica |
A fast driver circuit for single-photon sensors. |
Microelectronics Journal |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Energy Consumption in RC Tree Circuits. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Delay uncertainty due to supply variations in static and dynamic full adders. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, Melita Pennisi, Salvatore Pennisi |
Analysis and evaluation of harmonic distortion in the tunnel diode oscillator. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Nanometer MCML gates: models and design considerations. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi |
Active reversed nested Miller compensation for three-stage amplifiers. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Design techniques for low-power cascaded CML gates. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, P. Tommasino, Alessandro Trifiletti |
Optimized design of source coupled logic gates in GaAs HEMT technology. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosario Mita, Gaetano Palumbo, Salvatore Pennisi |
Well-defined design procedure for a three-stage CMOS OTA. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Evaluation of energy consumption in RC ladder circuits driven by a ramp input. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Giustolisi, Gaetano Palumbo |
Sigma-Delta A/D fuzzy converter. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Walter Aloisi, Stello Matteo Billé, Gaetano Palumbo |
Low-voltage linear voltage regulator suitable for memories. |
ISCAS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, Salvatore Pennisi |
Harmonic distortion in three-stage nested-Miller-compensated amplifiers. |
ISCAS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
A gate-level strategy to design Carry Select Adders. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Massimo Alioto, Rosario Mita, Gaetano Palumbo |
Performance evaluation of the low-voltage CML D-latch topology. |
Integration |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Design of MUX, XOR and D-latch SCL gates. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo |
A 1-V CMOS output stage with high linearity. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Giustolisi, Gaetano Palumbo |
A new method for evaluating harmonic distortion in push-pull output stages. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Giustolisi, Gaetano Palumbo |
A novel 1-V class-AB transconductor for improving speed performance in SC applications. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosario Mita, Gaetano Palumbo, Salvatore Pennisi |
Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo |
Design of low-voltage low-power SC filters for high-frequency applications. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Analysis and comparison on full adder block in submicron technology. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosario Mita, Gaetano Palumbo |
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
An Approach to Energy Consumption Modeling in RC Ladder Circuits. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo 0002, Agatino Pennisi, Gaetano Palumbo |
Low Power Strategy for a TFT Controller. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Giustolisi, Gaetano Palumbo |
Analysis of power supply noise attenuation in a PTAT current source. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, F. Pappalardo, S. Sannella |
Evaluation on power reduction applying gated clock approaches. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Power-delay trade-offs in SCL gates. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo |
Analysis and optimization of gain-boosted telescopic amplifiers. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Power estimation in adiabatic circuits: a simple and accurate model. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo |
CML ring oscillators: oscillation frequency. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, D. Pappalardo, M. Gaibotti |
Modeling and minimization of power consumption in charge pump circuits. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosario Mita, Gaetano Palumbo, Salvatore Pennisi |
Reversed nested Miller compensation with current follower. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Giustolisi, Gaetano Palumbo |
Detailed frequency analysis of power supply rejection in Brokaw bandgap. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton |
Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. |
PATMOS |
2000 |
DBLP BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Highly accurate and simple models for CML and ECL gates. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianluca Giustolisi, Giovanni Palmisano, Gaetano Palumbo, C. Strano |
A Novel 1.5-V Cmos Mixer. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo |
Novel Simple Models Of Cml Propagation Delay. (PDF / PS) |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Giuseppe Di Cataldo, Giovanni Palmisano, Gaetano Palumbo |
A CMOS CCII+. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Giuseppe Di Cataldo, Gaetano Palumbo |
Optimized Design of 4 Stage Dickson Voltage Multiplier. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Gaetano Palumbo |
Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling time. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Giovanni Palmisano, Gaetano Palumbo, Salvatore Pennisi |
A High-Accuracy High-Speed CMOS Current Comparator. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
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