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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 9 keywords
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Results
Found 25 publication records. Showing 25 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose |
An Energy-Efficient Memristive Threshold Logic Circuit.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose |
Design Considerations for Multilevel CMOS/Nano Memristive Memory. |
JETC |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino |
Leveraging Memristive Systems in the Construction of Digital Logic Circuits. |
Proceedings of the IEEE |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose |
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. |
IEEE Trans. on Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Aamir Zia, Sachhidh Kannan, H. Jonathan Chao, Garrett S. Rose |
3D NOC for many-core processors. |
Microelectronics Journal |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Shamik Das, Garrett S. Rose |
Introduction to Special Issue: Highlights of NANOARCH'09. |
JETC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose |
An Approach to Tolerate Process Related Variations in Memristor-Based Applications. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose |
Parallel memristors: Improving variation tolerance in memristive digital circuits. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Garrett S. Rose, Robinson E. Pino, Qing Wu |
Exploiting memristance for low-energy neuromorphic computing hardware. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Garrett S. Rose |
A read-monitored write circuit for 1T1M multi-level memristor memories. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Sachhidh Kannan, Garrett S. Rose |
A hierarchical 3-D floorplanning algorithm for many-core CMP networks. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Garrett S. Rose, Robinson E. Pino, Qing Wu |
A low-power memristive neuromorphic circuit utilizing a global/local training mechanism. |
IJCNN |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang 0003 |
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
CMOS/nano, memristor, multi level memories |
| 1 | Garrett S. Rose |
Overview: Memristive devices, circuits and systems. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon |
Inversion schemes for sublithographic programmable logic arrays. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Yongji Jiang, Garrett S. Rose |
A dual-MOSFET equivalent resistor thermal sensor. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
integrated circuits, dynamic thermal management, vlsi, temperature sensors |
| 1 | Harika Manem, Garrett S. Rose |
The effects of logic partitioning in a majority logic based CMOS-NANO FPGA. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
cmos-nano, fpga |
| 1 | Xiaofei Guo, Shunting Lin, Wael Refai, Garrett S. Rose |
Non-overlapping transition encoding for global on-chip interconnect. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Peter C. Paliwoda, Garrett S. Rose |
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
PMLA, FPGA, hybrid |
| 1 | Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan |
Designing CMOS/molecular memories while considering device parameter variations. |
JETC |
2007 |
DBLP DOI BibTeX RDF |
CMOS, nanotechnology, molecular electronics |
| 1 | Nadine Gergel-Hackett, Garrett S. Rose, Peter C. Paliwoda, Christina A. Hacker, Curt A. Richter |
On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
hybrid circuits, molecular electronics |
| 1 | Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour |
Design approaches for hybrid CMOS/molecular memory based on experimental device data. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Garrett S. Rose, Mircea R. Stan |
A programmable majority logic array using molecular scale electronics. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler |
Hybrid CMOS/Molecular Electronic Circuits. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan |
Large-signal two-terminal device model for nanoelectronic circuit analysis. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
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