Search results for "Gary S. Tyson"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yue Li, Gary S. Tyson, Jinfeng Zhang	Effect of sequences on the shape of protein energy landscapes.	BCB	2010	DBLP DOI BibTeX RDF
1	Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson	Practical exhaustive optimization phase order exploration and evaluation.	TACO	2009	DBLP DOI BibTeX RDF	exhaustive search, Phase ordering, iterative compilation
1	Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson	Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.	T. HiPEAC	2009	DBLP DOI BibTeX RDF
1	Paul E. West, Yuval Peress, Gary S. Tyson, Sally A. McKee	Core monitors: monitoring performance in multicore processors.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	scheduling, debugging, profiling, multicore, cache coherency, performance monitoring, realtime
1	Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson	Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE).	LCTES	2009	DBLP DOI BibTeX RDF	l0/filter cache, lookahead instruction fetch engine (life), tagless hit instruction cache (th-ic)
1	Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy Kurian John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson	Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education	CoRR	2008	DBLP BibTeX RDF
1	David B. Whalley, Gary S. Tyson	Enhancing the effectiveness of utilizing an instruction register file.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy K. John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson	Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education.	CollaborateCom	2008	DBLP DOI BibTeX RDF	simulation, Grid computing, virtualization, computer architecture, collaborative environments
1	Michael J. Geiger, Sally A. McKee, Gary S. Tyson	Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems.	T. HiPEAC	2007	DBLP DOI BibTeX RDF
1	Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson	Evaluating Heuristic Optimization Phase Order Search Algorithms.	CGO	2007	DBLP DOI BibTeX RDF
1	Stephen Hines, David B. Whalley, Gary S. Tyson	Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache.	MICRO	2007	DBLP DOI BibTeX RDF
1	Chris Zimmer, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley	Facilitating compiler optimizations through the dynamic mapping of alternate register structures.	CASES	2007	DBLP DOI BibTeX RDF	register queues, compiler optimizations, software pipelining
1	Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson	Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems.	HiPEAC	2007	DBLP DOI BibTeX RDF
1	Stephen Roderick Hines, Gary S. Tyson, David B. Whalley	Addressing instruction fetch bottlenecks by using an instruction register file.	LCTES	2007	DBLP DOI BibTeX RDF	L0/filter cache, instruction packing, instruction register file
1	Allen C. Cheng, Gary S. Tyson	High-quality ISA synthesis for low-power cache designs in embedded microprocessors.	IBM Journal of Research and Development	2006	DBLP DOI BibTeX RDF
1	Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson	Exhaustive Optimization Phase Order Space Exploration.	CGO	2006	DBLP DOI BibTeX RDF
1	Stephen Hines, David B. Whalley, Gary S. Tyson	Adapting compilation techniques to enhance the packing of instructions into registers.	CASES	2006	DBLP DOI BibTeX RDF	instruction packing, instruction register file, compiler optimizations
1	William C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson	Reducing the cost of conditional transfers of control by using comparison specifications.	LCTES	2006	DBLP DOI BibTeX RDF	optimization, compiler, comparison, branch
1	Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson	In search of near-optimal optimization phase orderings.	LCTES	2006	DBLP DOI BibTeX RDF	genetic algorithms, exhaustive search, phase ordering
1	Allen C. Cheng, Gary S. Tyson	An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Low-power design, reconfigurable hardware, real-time and embedded systems, energy-aware systems, instruction set design
1	Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley	Improving Program Efficiency by Packing Instructions into Registers.	ISCA	2005	DBLP DOI BibTeX RDF
1	Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge	PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis.	ISPASS	2005	DBLP DOI BibTeX RDF
1	Stephen Hines, Gary S. Tyson, David B. Whalley	Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows.	MICRO	2005	DBLP DOI BibTeX RDF
1	Michael J. Geiger, Sally A. McKee, Gary S. Tyson	Drowsy region-based caches: minimizing both dynamic and static power dissipation.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	region-based caches, energy-aware design, drowsy caches
1	Michael J. Geiger, Sally A. McKee, Gary S. Tyson	Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation.	HiPEAC	2005	DBLP DOI BibTeX RDF
1	Viji Srinivasan, Edward S. Davidson, Gary S. Tyson	A Prefetch Taxonomy.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Prefetch algorithms, cache memory systems
1	Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge	FITS: framework-based instruction-set tuning synthesis for embedded application specific processors.	DAC	2004	DBLP DOI BibTeX RDF	16-bit ISA, instruction synthesis, low-power, energy efficient, embedded processor, reconfigurable processors, ASP, instruction encoding, configurable architecture, code density
1	Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens	Improving Bandwidth Utilization using Eager Writeback.	J. Instruction-Level Parallelism	2001	DBLP BibTeX RDF
1	Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak	Branch History Guided Instruction Prefetching.	HPCA	2001	DBLP DOI BibTeX RDF
1	Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson	Stack Value File: Custom Microarchitecture for the Stack.	HPCA	2001	DBLP DOI BibTeX RDF
1	Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson	Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme.	ICCD	2001	DBLP BibTeX RDF
1	Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson	Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining.	IEEE PACT	2000	DBLP DOI BibTeX RDF
1	Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson	Improving BTB performance in the presence of DLLs.	MICRO	2000	DBLP DOI BibTeX RDF
1	Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens	Eager writeback - a technique for improving bandwidth utilization.	MICRO	2000	DBLP DOI BibTeX RDF
1	Hsien-Hsin S. Lee, Gary S. Tyson	Region-based caching: an energy-delay efficient memory architecture for embedded processors.	CASES	2000	DBLP DOI BibTeX RDF
1	Matt Postiff, Gary S. Tyson, Trevor N. Mudge	Performance Limits of Trace Caches.	J. Instruction-Level Parallelism	1999	DBLP BibTeX RDF
1	Gary S. Tyson, Todd M. Austin	Memory Renaming: Fast, Early and Accurate Processing of Memory Communication.	International Journal of Parallel Programming	1999	DBLP DOI BibTeX RDF
1	Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson	Active Management of Data Caches by Exploiting Reuse Information.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Multilateral cache, reuse information, active management
1	Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin	Classifying load and store instructions for memory renaming.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF
1	Sangwook P. Kim, Gary S. Tyson	Analyzing the Working Set Characteristics of Branch Execution.	MICRO	1998	DBLP BibTeX RDF
1	Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson	mlcache: A Flexible Multi-Lateral Cache Simulator. (PDF / PS)	MASCOTS	1998	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens	Utilizing Reuse Information in Data Cache Management.	International Conference on Supercomputing	1998	DBLP DOI BibTeX RDF	effective address, multi-lateral caches, program counter
1	Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun	Managing data caches using selective cache line replacement.	International Journal of Parallel Programming	1997	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin	On High-Bandwidth Data Cache Design for Multi-Issue Processors.	MICRO	1997	DBLP BibTeX RDF	Locality-Based Interleaving, Multiporting, High-Bandwidth Data Supply, Multi-Bank Caches
1	Gary S. Tyson, Todd M. Austin	Improving the Accuracy and Performance of Memory Communication Through Renaming.	MICRO	1997	DBLP BibTeX RDF	data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation
1	Gary S. Tyson, Matthew K. Farrens	Evaluating the Effects of Predicated Execution on Branch Prediction.	International Journal of Parallel Programming	1996	DBLP BibTeX RDF
1	Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun	A modified approach to data cache management.	MICRO	1995	DBLP DOI BibTeX RDF
1	Gary S. Tyson, Matthew K. Farrens	Code scheduling for multiple instruction stream architectures.	International Journal of Parallel Programming	1994	DBLP DOI BibTeX RDF
1	Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun	A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors.	ISCA	1994	DBLP DOI BibTeX RDF
1	Gary S. Tyson	The effects of predicated execution on branch prediction.	MICRO	1994	DBLP DOI BibTeX RDF	HP-RISC, Pentium, high-performance, ATOM, branch prediction, predication, PowerPC, Alpha
1	Gary S. Tyson, Matthew K. Farrens	Techniques for extracting instruction level parallelism on MIMD architectures.	MICRO	1993	DBLP DOI BibTeX RDF
1	Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun	MISC: a Multiple Instruction Stream Computer.	MICRO	1992	DBLP DOI BibTeX RDF
1	Matthew K. Farrens, Arvin Park, Gary S. Tyson	Modifying VM hardware to reduce address pin requirements.	MICRO	1992	DBLP DOI BibTeX RDF

Publications of "Gary S. Tyson" ( http://dblp.L3S.de/Authors/Gary_S._Tyson )