| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging reversible circuits.  |
Integration  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Md. Mazder Rahman, Gerhard W. Dueck, Anindita Banerjee |
Optimization of Reversible Circuits Using Reconfigured Templates. |
RC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hadi Hosseini, Gerhard W. Dueck |
Toffoli Gate Implementation Using the Billiard Ball Model. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
Toffoli Gates, Billiard Ball Model, Logic Design, Reversible Logic |
| 1 | Yasaman Sanaee, Gerhard W. Dueck |
ESOP-Based Toffoli Network Generation with Transformations. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
Toffoli Gates, Logic Design, Reversible Logic, ESOP |
| 1 | Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Synthesizing multiplier in reversible logic. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Window optimization of reversible and quantum circuits. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gerhard W. Dueck |
Editorial. |
Multiple-Valued Logic and Soft Computing |
2009 |
DBLP BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Synthesis of Elementary Quantum Gate Circuits. |
Multiple-Valued Logic and Soft Computing |
2009 |
DBLP BibTeX RDF |
|
| 1 | D. Michael Miller, Robert Wille, Gerhard W. Dueck |
Synthesizing Reversible Circuits for Irreversible Functions. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
Reversible Logic Synthesis with Output Permutation. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging of Toffoli networks. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne |
Quantum Circuit Simplification and Level Compaction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nathan O. Scott, Gerhard W. Dueck |
Pairwise decomposition of toffoli gates in a quantum circuit. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
elementary quantum gates, synthesis, minimization, reversible logic, quantum circuits |
| 1 | Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Benchmarks, Synthesis, Reversible Logic |
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Synthesis, Boolean Satisfiability, Reversible Logic |
| 1 | Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
Quantified Synthesis of Reversible Logic. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Techniques for the synthesis of reversible Toffoli networks. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
reversible logic synthesis, quantum computing, circuit optimization |
| 1 | Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
Exact sat-based toffoli network synthesis. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
synthesis, minimization, boolean satisfiability, reversible logic, quantum circuits |
| 1 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Toffoli network synthesis with templates. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Synthesis of Fredkin-Toffoli reversible networks. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck |
Quantum Circuit Simplification Using Templates. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dmitri Maslov, Gerhard W. Dueck |
Reversible cascades with minimal garbage. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov |
A Synthesis Method for MVL Reversible Logi. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Simplification of Toffoli Networks via Templates. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck |
A transformation based algorithm for reversible logic synthesis. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
templates, minimization, reversible logic, quantum circuits |
| 1 | D. Michael Miller, Gerhard W. Dueck |
On the Size of Multiple-Valued Decision Diagrams. (PDF / PS) |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Fredkin/Toffoli Templates for Reversible Logic Synthesis. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ping Wang, Gerhard W. Dueck, S. MacMillan |
Using simulated annealing to construct extremal graphs. |
Discrete Mathematics |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko |
On the number of generators for transeunt triangles. |
Discrete Applied Mathematics |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich |
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko |
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. (PDF / PS) |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
fixed polarity Reed-Muller expression, symmetric functions, MVL functions |
| 1 | Gerhard W. Dueck, Mou Hu, Blair Fraser |
A Super Switch Algebra for Quantum Device Based Systems. (PDF / PS) |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Blair Fraser, Gerhard W. Dueck |
Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. (PDF / PS) |
ISMVL |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Gerhard W. Dueck, Jon T. Butler |
Multiple-Valued Logic Operations with Universal Literals. |
ISMVL |
1994 |
DBLP BibTeX RDF |
|
| 1 | Gerhard W. Dueck |
Direct Cover MVL Minimization with Cost-Tables. |
ISMVL |
1992 |
DBLP BibTeX RDF |
|
| 1 | Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler |
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. |
ISMVL |
1992 |
DBLP BibTeX RDF |
|
| 1 | Gerhard W. Dueck, G. H. John van Rees |
On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. |
ISMVL |
1991 |
DBLP BibTeX RDF |
|
| 1 | Gerhard W. Dueck, D. Michael Miller |
RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. |
ISMVL |
1990 |
DBLP BibTeX RDF |
|
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