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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 6 keywords
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Results
Found 13 publication records. Showing 13 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Amir Kaivani, Ghassem Jaberipur |
Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture.  |
Comput. J.  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Amir Kaivani, Adel Hosseiny, Ghassem Jaberipur |
Improving the speed of decimal division. |
IET Computers & Digital Techniques |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Saeid Gorgin, Ghassem Jaberipur |
A Family of High Radix Signed Digit Adders. |
IEEE Symposium on Computer Arithmetic |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin |
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
Adder/subtractor, redundant format, computer arithmetic, floating point, rounding, signed-digit number system |
| 1 | Ghassem Jaberipur, Saeid Gorgin |
An improved maximally redundant signed digit adder. |
Computers & Electrical Engineering |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Amir Kaivani, Ghassem Jaberipur |
Fully redundant decimal addition and subtraction using stored-unibit encoding. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Saeid Gorgin, Ghassem Jaberipur |
A fully redundant decimal adder and its application in parallel decimal multipliers. |
Microelectronics Journal |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ghassem Jaberipur, Amir Kaivani |
Improving the Speed of Parallel Decimal Multiplication. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Saeid Gorgin, Ghassem Jaberipur |
Fully Redundant Decimal Arithmetic. |
IEEE Symposium on Computer Arithmetic |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ghassem Jaberipur, Behrooz Parhami |
Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues. |
IEEE Symposium on Computer Arithmetic |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ghassem Jaberipur, Behrooz Parhami |
Constant-time addition with hybrid-redundant numbers: Theory and implementations. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Ghassem Jaberipur, Amir Kaivani |
Binary-coded decimal digit multipliers. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi |
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. |
VLSI Signal Processing |
2006 |
DBLP DOI BibTeX RDF |
(4,2)-compressor, digit set, signed digit, computer arithmetic, redundant number system, carry-free addition |
Displaying result #1 - #13 of 13 (100 per page; Change: )
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