Search results for "Giovanni De Micheli"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli	Inter-Plane Communication Methods for 3-D ICs.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Davide Sacchetto, Giovanni De Micheli, Yusuf Leblebici	Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review.	Proceedings of the IEEE	2012	DBLP DOI BibTeX RDF
1	Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli	A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands.	J. Electrical and Computer Engineering	2012	DBLP DOI BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De Micheli	The combined effect of process variations and power supply noise on clock skew and jitter.	ISQED	2012	DBLP DOI BibTeX RDF
1	Giovanni De Micheli	Engineering complex systems for health, security and the environment.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Cheng Zhang, Vasilis F. Pavlidis, Giovanni De Micheli	Voltage propagation method for 3-D power grid analysis.	DATE	2012	DBLP BibTeX RDF
1	M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli	An Efficient Gate Library for Ambipolar CNTFET Logic.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Wenqi You, Nicolas Widmer, Giovanni De Micheli	Personalized modeling for drug concentration prediction using Support Vector Machine.	BMEI	2011	DBLP DOI BibTeX RDF
1	Daniela De Venuto, Sandro Carrara, Andrea Cavallini, Giovanni De Micheli	pH sensing with temperature compensation in a Molecular Biosensor for drugs detection.	ISQED	2011	DBLP DOI BibTeX RDF
1	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	A DRAM Centric NoC Architecture and Topology Design Approach.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli	A Simulation Based Buffer Sizing Algorithm for Network on Chips.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Francesco Zanini, David Atienza, Giovanni De Micheli	Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli	Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli	CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Jaume Joven, Per Strict, David Castells-Rufas, Akash Bagdia, Giovanni De Micheli, Jordi Carrabina	HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs.	SIES	2011	DBLP DOI BibTeX RDF
1	Giovanni De Micheli, S. S. Ghoreishizadeh, Cristina Boero, F. Valgimigli, Sandro Carrara	An integrated platform for advanced diagnostics.	DATE	2011	DBLP DOI BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Analytical heat transfer model for thermal through-silicon vias.	DATE	2011	DBLP BibTeX RDF
1	Giovanni De Micheli	Logic synthesis and physical design: Quo vadis?	DATE	2011	DBLP BibTeX RDF
1	Francesco Zanini, David Atienza, Luca Benini, Giovanni De Micheli	Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Skew variability in 3-D ICs with multiple clock domains.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici	Alternative design methodologies for the next generation logic switch.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Sandro Carrara, Andrea Cavallini, Yusuf Leblebici, Giovanni De Micheli, Vijayender Bhalla, Francesco Valle, Bruno Samorì, Luca Benini, Bruno Riccò, Inger Vikholm-Lundin, Tony Munter	Capacitance DNA bio-chips improved by new probe immobilization strategies.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Francesco Zanini, David Atienza, Giovanni De Micheli, Stephen P. Boyd	Online convex optimization-based algorithm for thermal management of MPSoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	management, MPSoCs, convex optimization, online, thermal
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Process-induced skew variation for scaled 2-D and 3-D ICs.	SLIP	2010	DBLP DOI BibTeX RDF
1	Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini	Networks on Chips: from research to products.	DAC	2010	DBLP DOI BibTeX RDF	SoC, system on chip, network on chip, NoC
1	Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra	Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.	DAC	2010	DBLP DOI BibTeX RDF	CNT correlation, carbon nanotube, yield optimization, CNT
1	Srinivasan Murali, Luca Benini, Giovanni De Micheli	Design of networks on chips for 3D ICs.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Michele Lombardi, Luca Benini, Abhishek Garg, Giovanni De Micheli	Methods for Designing Reliable Probe Arrays.	BIBE	2010	DBLP DOI BibTeX RDF	Probe based sensors, Optimization, Microarrays, SAT, ILP
1	Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Piero Perlo, Andreas Wild, Roberto Zafalon	Panel: First commandment at least, do nothing well!	DATE	2010	DBLP BibTeX RDF
1	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	A method to remove deadlocks in Networks-on-Chips with Wormhole flow control.	DATE	2010	DBLP BibTeX RDF
1	M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli	Power consumption of logic circuits in ambipolar carbon nanotube technology.	DATE	2010	DBLP BibTeX RDF
1	Francesco Zanini, David Atienza, Colin N. Jones, Giovanni De Micheli	Temperature sensor placement in thermal management systems for MPSoCs.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici	Memristive devices fabricated with silicon nanowire schottky barrier transistors.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Nikolaos Archontas, Julius Georgiou, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli	Characterization of memristive Poly-Si Nanowires via empirical physical modelling.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici	Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Shashikanth Bobba, Sandro Carrara, Giovanni De Micheli	Design of a CNFET array for sensing and control in P450 based biochips for multiple drug detection.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Francesco Zanini, Colin N. Jones, David Atienza, Giovanni De Micheli	Multicore thermal management using approximate explicit model predictive control.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Ioannis Tsioutsios, Vasilis F. Pavlidis, Giovanni De Micheli	Physical design tradeoffs in power distribution networks for 3-D ICs.	ICECS	2010	DBLP DOI BibTeX RDF
1	Michele De Marchi, Shashikanth Bobba, M. Haykel Ben Jamaa, Giovanni De Micheli	Synthesis of regular computational fabrics with ambipolar CNTFET technology.	ICECS	2010	DBLP DOI BibTeX RDF
1	Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli	Performance analysis of 3-D monolithic integrated circuits.	3DIC	2010	DBLP DOI BibTeX RDF
1	Jaume Joven, Andrea Marongiu, Federico Angiolini, Luca Benini, Giovanni De Micheli	Exploring programming model-driven QoS support for NoC-based platforms.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Abhishek Garg, Kartik Mohanram, Alessandro Di Cara, Giovanni De Micheli, Ioannis Xenarios	Modeling stochasticity and robustness in gene regulatory networks.	Bioinformatics	2009	DBLP DOI BibTeX RDF
1	Fabrizio Mulas, David Atienza, Andrea Acquaviva, Salvatore Carta, Luca Benini, Giovanni De Micheli	Thermal Balancing Policy for Multiprocessor Stream Computing Platforms.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Giovanni De Micheli	An Outlook on Design Technologies for Future Integrated Systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Almir Mutapcic, Stephen P. Boyd, Srinivasan Murali, David Atienza, Giovanni De Micheli, Rajesh Gupta	Processor Speed Control With Thermal Constraints.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Giovanni De Micheli	Power distribution paths in 3-D ICS.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	power distribution network, 3-D ICS, 3-D integration, through silicon vias
1	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	NoC topology synthesis for supporting shutdown of voltage islands in SoCs.	DAC	2009	DBLP DOI BibTeX RDF	shutdown, topology, NoC, leakage power, voltage islands
1	M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli	Decoding nanowire arrays fabricated with the multi-spacer patterning technique.	DAC	2009	DBLP DOI BibTeX RDF	MSPT, spacer technique, decoder, emerging technologies, crossbar, nanowires
1	M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli	Complete nanowire crossbar framework optimized for the multi-spacer patterning technique.	CASES	2009	DBLP DOI BibTeX RDF	MSPT, spacer technique, decoder, emerging technologies, gray code, crossbars, nanowires
1	Francesco Zanini, David Atienza, Giovanni De Micheli	A control theory approach for thermal balancing of MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli	A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli	Synthesis of networks on chips for 3D systems on chips.	ASP-DAC	2009	DBLP DOI BibTeX RDF	topology synthesis, networks on chip, 3D, application-specific
1	Eugène David Ngangue Ndih, Nadia Khaled, Giovanni De Micheli	An Analytical Model for the Contention Access Period of the Slotted IEEE 802.15.4 with Service Differentiation.	ICC	2009	DBLP DOI BibTeX RDF
1	Francisco J. Rincón, Laura Gutiérrez, Mónica Jiménez, Víctor Díaz, Nadia Khaled, David Atienza, Marcos Sanchez-Elez, Joaquín Recas, Giovanni De Micheli	Implementation of an Automated ECG-based Diagnosis Algorithm for a Wireless Body Sensor Plataform.	BIODEVICES	2009	DBLP BibTeX RDF
1	Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli	Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.	DATE	2009	DBLP BibTeX RDF
1	Marco Casale-Rossi, Giovanni De Micheli	Panel session - Consolidation, a modern "Moor of Venice" tale.	DATE	2009	DBLP BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii	Physically clustered forward body biasing for variability compensation in nanometer CMOS design.	DATE	2009	DBLP BibTeX RDF
1	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips.	DATE	2009	DBLP BibTeX RDF
1	M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli	Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis.	DATE	2009	DBLP BibTeX RDF
1	Sandro Carrara, Cristina Boero, Giovanni De Micheli	Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing.	NanoNet	2009	DBLP DOI BibTeX RDF	Quantum Wires, Gold Nano-Particles, Oxidases, Cytochromes, Electrochemical detection, Carbon Nanotubes, Quantum Dots
1	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.	NanoNet	2009	DBLP DOI BibTeX RDF	timing optimization, on-chip interconnect, repeater insertion, 3-D ICs
1	Dara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad	A method for calculating hard QoS guarantees for Networks-on-Chip.	ICCAD	2009	DBLP BibTeX RDF
1	Abhishek Garg, Alessandro Di Cara, Ioannis Xenarios, Luis Mendoza, Giovanni De Micheli	Synchronous versus asynchronous modeling of gene regulatory networks.	Bioinformatics	2008	DBLP DOI BibTeX RDF
1	Terry Tao Ye, Giovanni De Micheli	On-chip implementation of multiprocessor networks and switch fabrics.	IJES	2008	DBLP DOI BibTeX RDF
1	M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli	Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Elisa Ficarra, Giovanni De Micheli, Sungroh Yoon, Luca Benini, Enrico Macii	Joint co-clustering: Co-clustering of genomic and clinical bioimaging data.	Computers & Mathematics with Applications	2008	DBLP DOI BibTeX RDF
1	Giovanni De Micheli	Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo	Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.	Integration	2008	DBLP DOI BibTeX RDF
1	David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli	Network-on-Chip design and synthesis outlook.	Integration	2008	DBLP DOI BibTeX RDF
1	Giovanni De Micheli	System-level design technologies for heterogeneous distributed systems.	SBCCI	2008	DBLP DOI BibTeX RDF	integrated circuits design
1	M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli	Programmable logic circuits based on ambipolar CNFET.	DAC	2008	DBLP DOI BibTeX RDF	CNFET, FPGA, PLA, carbon nanotube
1	David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijaykrishnan Narayanan	Reliability-aware design for nanometer-scale devices.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Giovanni De Micheli	Designing Micro/Nano Systems for a Safer and Healthier Tomorrow.	DATE	2008	DBLP DOI BibTeX RDF
1	Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Luca Benini, Giovanni De Micheli	Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization.	DATE	2008	DBLP DOI BibTeX RDF
1	Francisco J. Rincón, Michele Paselli, Joaquín Recas, Qin Zhao, Marcos Sanchez-Elez, David Atienza, Julien Penders, Giovanni De Micheli	OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks.	DATE	2008	DBLP DOI BibTeX RDF
1	Fabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, Andrea Acquaviva, Luca Benini, David Atienza, Giovanni De Micheli	Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures.	DATE	2008	DBLP DOI BibTeX RDF
1	Alessandro Di Cara, Abhishek Garg, Giovanni De Micheli, Ioannis Xenarios, Luis Mendoza	Dynamic simulation of regulatory networks using SQUAD.	BMC Bioinformatics	2007	DBLP DOI BibTeX RDF
1	Sungroh Yoon, Jessica C. Ebert, Eui-Young Chung, Giovanni De Micheli, Russ B. Altman	Clustering protein environments for function prediction: finding PROSITE motifs in 3D.	BMC Bioinformatics	2007	DBLP DOI BibTeX RDF
1	Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli	A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Alex E. Susu, Michele Magno, Andrea Acquaviva, David Atienza, Giovanni De Micheli	Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.	T. HiPEAC	2007	DBLP DOI BibTeX RDF	FPGA, Markov chains, energy harvesting, probabilistic model checking, Wireless Sensor Nodes
1	Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini	Bringing NoCs to 65 nm.	IEEE Micro	2007	DBLP DOI BibTeX RDF	network on chip, low-power design, power management, multicore architectures, on-chip interconnection networks, design aids, deep submicron design
1	David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida	HW-SW emulation framework for temperature-aware design in MPSoCs.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Thermal-aware design, FPGA, emulation, MPSoC, temperature
1	Srinivasan Murali, Luca Benini, Giovanni De Micheli	An Application-Specific Design Methodology for On-Chip Crossbar Generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli	Timing-Error-Tolerant Network-on-Chip Design Methodology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Srinivasan Murali, Giovanni De Micheli	An Application-Specific Design Methodology for STbus Crossbar Generation	CoRR	2007	DBLP BibTeX RDF
1	Sungroh Yoon, Luca Benini, Giovanni De Micheli	Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics.	IEEE Transactions on Information Technology in Biomedicine	2007	DBLP DOI BibTeX RDF
1	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Tajana Simunic Rosing, Kresimir Mihic, Giovanni De Micheli	Power and Reliability Management of SoCs.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Giovanni De Micheli	Design Technologies for Networks on Chips.	NOCS	2007	DBLP DOI BibTeX RDF
1	Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini	NoC Design and Implementation in 65nm Technology.	NOCS	2007	DBLP DOI BibTeX RDF
1	Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias	Multi-processor operating system emulation framework with thermal feedback for systems-on-chip.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	thermal studies, FPGA, operating system, emulation, MPSoC
1	Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli	Early wire characterization for predictable network-on-chip global interconnects.	SLIP	2007	DBLP DOI BibTeX RDF	early wire characterization, design methodology, NoCs, global interconnects
1	Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli	Interactive presentation: Improving the fault tolerance of nanometric PLA designs.	DATE	2007	DBLP DOI BibTeX RDF
1	Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo	Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Abhishek Garg, Ioannis Xenarios, Luis Mendoza, Giovanni De Micheli	An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and in silico Gene Perturbation Experiments.	RECOMB	2007	DBLP DOI BibTeX RDF
1	M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli	Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Giovanni De Micheli	Temperature-aware processor frequency assignment for MPSoCs using convex optimization.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	temperature-aware, MPSoCs, convex optimization, thermal
1	Ayse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici	Analysis and Optimization of MPSoC Reliability.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF

Publications of "Giovanni De Micheli" ( http://dblp.L3S.de/Authors/Giovanni_De_Micheli )