| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi |
Supporting Overcommitted Virtual Machines through Hardware Spin Detection.  |
IEEE Trans. Parallel Distrib. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Gagan Gupta, Gurindar S. Sohi |
Dataflow execution of sequential imperative programs on multicore architectures. |
MICRO |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi |
Dynamic heterogeneity and the need for multicore virtualization. |
Operating Systems Review |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi |
Mixed-mode multicore reliability. |
ASPLOS |
2009 |
DBLP DOI BibTeX RDF |
dual-modular redundancy, multicore |
| 1 | Matthew D. Allen, Srinath Sridharan, Gurindar S. Sohi |
Serialization sets: a dynamic dependence-based parallel execution model. |
PPOPP |
2009 |
DBLP DOI BibTeX RDF |
serialization sets, parallel computing, runtime system, serializer |
| 1 | Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi |
Adapting to intermittent faults in multicore systems. |
ASPLOS |
2008 |
DBLP DOI BibTeX RDF |
overcommitted system, intermittent faults |
| 1 | Philip M. Wells, Gurindar S. Sohi |
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again. |
HPCA |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi |
Adapting to Intermittent Faults in Future Multicore Systems. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jichuan Chang, Gurindar S. Sohi |
Cooperative cache partitioning for chip multiprocessors. |
ICS |
2007 |
DBLP DOI BibTeX RDF |
cooperative cache partitioning, multiple time-sharing partitions, QoS, fairness, CMP |
| 1 | Jichuan Chang, Gurindar S. Sohi |
Cooperative Caching for Chip Multiprocessors. |
ISCA |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saisanthosh Balakrishnan, Gurindar S. Sohi |
Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs. |
ISCA |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi |
Hardware support for spin management in overcommitted virtual machines. |
PACT |
2006 |
DBLP DOI BibTeX RDF |
virtual machines, chip multiprocessors, synchronization overhead |
| 1 | Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi |
Computation spreading: employing hardware migration to specialize CMP cores on-the-fly. |
ASPLOS |
2006 |
DBLP DOI BibTeX RDF |
dynamic specialization, cache locality |
| 1 | Allison L. Holloway, Gurindar S. Sohi |
Characterization of Problem Stores. |
Computer Architecture Letters |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi |
Speculative Incoherent Cache Protocols. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Adam Butts, Gurindar S. Sohi |
Use-Based Register Caching with Decoupled Indexing. |
ISCA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar S. Sohi |
Coherence decoupling: making use of incoherence. |
ASPLOS |
2004 |
DBLP DOI BibTeX RDF |
coherence decoupling, coherence misses, speculative cache lookup, false sharing |
| 1 | Gurindar S. Sohi |
Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation. |
MICRO |
2004 |
DBLP BibTeX RDF |
|
| 1 | Paramjit S. Oberoi, Gurindar S. Sohi |
Parallelism in the Front-End. (PDF / PS) |
ISCA |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saisanthosh Balakrishnan, Gurindar S. Sohi |
Exploiting Value Locality in Physical Register Files. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Moshovos, Gurindar S. Sohi |
Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
memory dependence prediction, cache, dynamic optimization, load |
| 1 | J. Adam Butts, Gurindar S. Sohi |
Dynamic dead-instruction detection and elimination. |
ASPLOS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Roth, Gurindar S. Sohi |
A quantitative framework for automated pre-execution thread selection. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig B. Zilles, Gurindar S. Sohi |
Master/slave speculative parallelization. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Adam Butts, Gurindar S. Sohi |
Characterizing and predicting value degree of use. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Paramjit S. Oberoi, Gurindar S. Sohi |
Out-of-Order Instruction Fetch Using Multiple Sequencers. (PDF / PS) |
ICPP |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Roth, Gurindar S. Sohi |
Squash Reuse via a Simplified Implementation of Register Integration. |
J. Instruction-Level Parallelism |
2001 |
DBLP BibTeX RDF |
|
| 1 | T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi |
Speculative Versioning Cache. |
IEEE Trans. Parallel Distrib. Syst. |
2001 |
DBLP DOI BibTeX RDF |
Speculative memory, snooping cache coherence protocols, speculative versioning, memory disambiguation |
| 1 | Gurindar S. Sohi, Amir Roth |
Speculative Multithreaded Processors. |
IEEE Computer |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig B. Zilles, Gurindar S. Sohi |
Execution-based prediction using speculative slices. |
ISCA |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi |
Microprocessors - 10 Years Back, 10 Years Ahead. |
Informatics |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig B. Zilles, Gurindar S. Sohi |
A Programmable Co-Processor for Profiling. |
HPCA |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Roth, Gurindar S. Sohi |
Speculative Data-Driven Multithreading. |
HPCA |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Moshovos, Gurindar S. Sohi |
Memory Dependence Prediction in Multimedia Applications. |
J. Instruction-Level Parallelism |
2000 |
DBLP BibTeX RDF |
|
| 1 | Gurindar S. Sohi |
Amir Roth: Speculative Multithreaded Processors. |
HiPC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig B. Zilles, Gurindar S. Sohi |
Understanding the backward slices of performance degrading instructions. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Roth, Gurindar S. Sohi |
Register integration: a simple and efficient implementation of squash reuse. |
MICRO |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Adam Butts, Gurindar S. Sohi |
A static power model for architects. |
MICRO |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Moshovos, Gurindar S. Sohi |
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. |
HPCA |
2000 |
DBLP DOI BibTeX RDF |
Scheduling, Cache, Memory, Instruction Level Parallelism |
| 1 | Andreas Moshovos, Gurindar S. Sohi |
Speculative Memory Cloaking and Bypassing. |
International Journal of Parallel Programming |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | T. N. Vijaykumar, Gurindar S. Sohi |
Task Selection for the Multiscalar Architecture. |
J. Parallel Distrib. Comput. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Roth, Gurindar S. Sohi |
Effective Jump-Pointer Prefetching for Linked Data Structures. |
ISCA |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi |
The Use of Multithreading for Exception Handling. (PDF / PS) |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Moshovos, Gurindar S. Sohi |
Read-After-Read Memory Dependence Prediction. (PDF / PS) |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Roth, Andreas Moshovos, Gurindar S. Sohi |
Improving virtual function call target prediction via dependence-based pre-computation. |
International Conference on Supercomputing |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Sriram Vajapeyam |
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. |
25 Years ISCA: Retrospectives and Reprints |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar |
Multiscalar Processors. |
25 Years ISCA: Retrospectives and Reprints |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Mateo Valero, Gurindar S. Sohi, Doug DeGroot (eds.) |
Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998 |
ISCA |
1998 |
DBLP BibTeX RDF |
|
| 1 | Gurindar S. Sohi (eds.) |
25 Years of the International Symposia on Computer Architecture (Selected Papers). |
ISCA Selected Papers |
1998 |
DBLP BibTeX RDF |
|
| 1 | Gurindar S. Sohi |
Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. |
25 Years ISCA: Retrospectives and Reprints |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi |
Retrospective: Multiscalar Processors. |
25 Years ISCA: Retrospectives and Reprints |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Avinash Sodani, Gurindar S. Sohi |
An Empirical Analysis of Instruction Repetition. |
ASPLOS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Roth, Andreas Moshovos, Gurindar S. Sohi |
Dependance Based Prefetching for Linked Data Structures. |
ASPLOS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Avinash Sodani, Gurindar S. Sohi |
Understanding the Differences Between Value Prediction and Instruction Reuse. |
MICRO |
1998 |
DBLP BibTeX RDF |
|
| 1 | T. N. Vijaykumar, Gurindar S. Sohi |
Task Selection for a Multiscalar Processor. |
MICRO |
1998 |
DBLP BibTeX RDF |
|
| 1 | Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi |
Speculative Versioning Cache. |
HPCA |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Doug Burger, James R. Goodman, Gurindar S. Sohi |
Memory Systems. |
The Computer Science and Engineering Handbook |
1997 |
DBLP BibTeX RDF |
|
| 1 | Avinash Sodani, Gurindar S. Sohi |
Dynamic Instruction Reuse. |
ISCA |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi |
Dynamic Speculation and Synchronization of Data Dependences. |
ISCA |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Moshovos, Gurindar S. Sohi |
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. |
MICRO |
1997 |
DBLP BibTeX RDF |
DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation |
| 1 | Manoj Franklin, Gurindar S. Sohi |
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Todd M. Austin, Gurindar S. Sohi |
High-Bandwidth Address Translation for Multiple-Issue Processors. |
ISCA |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi |
Streamlining Data Cache Access with Fast Address Calculation. |
ISCA |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar |
Multiscalar Processors. |
ISCA |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Todd M. Austin, Gurindar S. Sohi |
Zero-cycle loads: microarchitecture support for reducing load latency. |
MICRO |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Alvin R. Lebeck, Gurindar S. Sohi |
Request Combining in Multiprocessors with Arbitrary Interconnection Networks. |
IEEE Trans. Parallel Distrib. Syst. |
1994 |
DBLP DOI BibTeX RDF |
arbitrary interconnection networks, shared memory location, combining set, processor elements, simulationresults, parallel architectures, virtual machines, multiprocessors, message passing, multiprocessor interconnection networks, shared memory systems, design space, hot spots, message routing, parallel access, classification scheme, combining strategies |
| 1 | Todd M. Austin, Scott E. Breach, Gurindar S. Sohi |
Efficient Detection of All Pointer and Array Access Errors. |
PLDI |
1994 |
DBLP DOI BibTeX RDF |
C |
| 1 | Dionisios N. Pnevmatikatos, Gurindar S. Sohi |
Guarded Executing and Branch Prediction in Dynamic ILP Processors. |
ISCA |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi |
The anatomy of the register file in a multiscalar processor. |
MICRO |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi |
High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
high bandwidth interleaved memories, alternate interleaving schemes, vector processing systems, parallel processing, computer architecture, storage management, buffering, simulation study, access patterns, vector processors |
| 1 | Dionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi |
Control flow prediction for dynamic ILP processors. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | MenChow Chiang, Gurindar S. Sohi |
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
throughput-oriented environment, overall throughput, design choices, mean value analysis analytical models, trace-driven simulation analysis, cache block sizes, cache set associativity, multiprocessor throughput, performance evaluation, performance, multiprocessing systems, digital simulation, shared bus multiprocessors |
| 1 | Todd M. Austin, Gurindar S. Sohi |
Dynamic Dependency Analysis of Ordinary Programs. |
ISCA |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Franklin, Gurindar S. Sohi |
The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. |
ISCA |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Franklin, Gurindar S. Sohi |
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. |
MICRO |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu |
An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. |
ISCA |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Manoj Franklin |
High-Bandwidth Data Memory Systems for Superscalar Processors. |
ASPLOS |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | MenChow Chiang, Gurindar S. Sohi |
Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors. |
SIGMETRICS |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Steven L. Scott, Gurindar S. Sohi |
The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control. |
IEEE Trans. Parallel Distrib. Syst. |
1990 |
DBLP DOI BibTeX RDF |
tree saturation control, feedback control schemes, hot-spot accesses, feedback, feedback, multiprocessor interconnection networks, multiprocessing systems, multiprocessor systems, multistage interconnection networks |
| 1 | Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan |
Design and Analysis of a Gracefully Degrading Interleaved Memory System. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
gracefully degrading interleaved memory system, digital storage, fault tolerant computing, trace-driven simulation, interleaved memories, reconfiguration scheme |
| 1 | Gurindar S. Sohi |
Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Wei-Chung Hsu |
The use of intermediate memories for low-latency memory access in supercomputer scalar units. |
The Journal of Supercomputing |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain |
Scalable Shared-Memory Multiprocessor Architectures. |
IEEE Computer |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Mary K. Vernon, Rajeev Jog, Gurindar S. Sohi |
Performance Analysis of Hierarchical Cache-Consistent Multiprocessors. |
Perform. Eval. |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi |
Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
cache memory organization, high performance VLSI processors, tolerance of defects faults, linear RAMs, trace-driven simulation analysis, storage management chips, VLSI, yield, fault location, buffer storage, performance degradation, random-access storage, integrated memory circuits |
| 1 | Steven L. Scott, Gurindar S. Sohi |
Using Feedback to Control Tree Saturation in Multistage Interconnection Networks. |
ISCA |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Sriram Vajapeyam |
Tradeoffs in Instruction Format Design for Horizontal Architectures. |
ASPLOS |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | V. S. Madan, C.-J. Peng, Gurindar S. Sohi |
On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns. |
NACLP |
1989 |
DBLP BibTeX RDF |
|
| 1 | Gurindar S. Sohi, James E. Smith, James R. Goodman |
Restricted Fetch&Phi operations for parallel processing. |
ICS |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Manoj Franklin, Kewal K. Saluja |
A study of time-redundant fault tolerance techniques for high-performance pipelined computers. |
FTCS |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew R. Pleszkun, Gurindar S. Sohi |
The Performance Potential of Multiple Functional Unit Processors. |
ISCA |
1988 |
DBLP BibTeX RDF |
|
| 1 | Andrew R. Pleszkun, Gurindar S. Sohi |
Multiple instruction issue and single-chip processors. |
MICRO |
1988 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Sriram Vajapeyam |
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. |
ISCA |
1987 |
DBLP DOI BibTeX RDF |
|
| 1 | Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan |
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. |
ISCA |
1987 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson |
Features of the Structured Memory Access (SMA) Architecture. |
COMPCON |
1986 |
DBLP BibTeX RDF |
|
| 1 | Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel |
An Efficient LISP-Execution Architecture with a New Representation for List Structures. |
ISCA |
1985 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")