Search results for "Gwan Choi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson, Gwan Choi	Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yoon Seok Yang, Pankaj Bhagawat, Gwan Choi	Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system.	DAC	2011	DBLP DOI BibTeX RDF
1	Reeshav Kumar, Yoon Seok Yang, Gwan Choi	Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi	Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs.	NOCS	2010	DBLP DOI BibTeX RDF	asynchronous interconnect, NoC, GALS, on-chip networks
1	Pankaj Bhagawat, Rajballav Dash, Gwan Choi	Systolic like soft-detection architecture for 4×4 64-QAM MIMO system.	DATE	2009	DBLP BibTeX RDF
1	Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi	Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary	Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".	EURASIP J. Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi	Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi	SEU hardened clock regeneration circuits.	ISQED	2009	DBLP DOI BibTeX RDF
1	Pankaj Bhagawat, Rajballav Dash, Gwan S. Choi	Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study.	ASP-DAC	2009	DBLP DOI BibTeX RDF	fixed sphere decoding (FSD) algorithm, on-the-fly reconfigurability, ASIC, MIMO systems, 802.11n
1	Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam	Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Rohit Singhal, Gwan Choi, Rabi N. Mahapatra	Data Handling Limits of On-Chip Interconnects.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Pankaj Bhagawat, Rajballav Dash, Gwan Choi	Dynamically reconfigurable soft output MIMO detector.	ICCD	2008	DBLP DOI BibTeX RDF
1	Weihuang Wang, Gwan Choi	Speculative Energy Scheduling for LDPC Decoding.	ISQED	2007	DBLP DOI BibTeX RDF
1	Pankaj Bhagawat, Weihuang Wang, Momin Uppal, Gwan Choi, Zixiang Xiong, Mark B. Yeary, Alan Harris	An FPGA Implementation of Dirty Paper Precoder.	ICC	2007	DBLP DOI BibTeX RDF
1	Sanghoan Chang, Gwan Choi	Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Weihuang Wang, Gwan Choi	Minimum-energy LDPC decoder for real-time mobile application.	DATE	2007	DBLP DOI BibTeX RDF
1	Kiran K. Gunnam, Gwan Choi, Weihuang Wang, Mark B. Yeary	Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Mohammed Atiquzzaman	VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax.	ICC	2007	DBLP DOI BibTeX RDF
1	Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary	A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi	A design approach for radiation-hard digital electronics.	DAC	2006	DBLP DOI BibTeX RDF	radiation-hard, SEU
1	Sanghoan Chang, Gwan Choi	Timing Failure Analysis of Commercial CPUs Under Operating Stress.	DFT	2006	DBLP DOI BibTeX RDF
1	Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra	Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk.	ISQED	2006	DBLP DOI BibTeX RDF
1	Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra	Programmable LDPC Decoder Based on the Bubble-Sort Algorithm.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra	Information theoretic approach to address delay and reliability in long on-chip interconnects.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra	Quantized LDPC decoder design for binary symmetric channels.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Rajeshwary Tayade, Gwan Choi	Fast Simulation Technique for LDPC Code Analysis.	International Conference on Wireless Networks	2004	DBLP BibTeX RDF
1	Rohit Singhal, Gwan S. Choi, Nathan Mickler, Prabhavati Koteeswaran	Scaleable check node centric architecture for LDPC decoder.	ISCAS	2004	DBLP BibTeX RDF
1	Anand Selvarathinam, Gwan Choi, Krishna Narayanan, Achal Prabhakar, Euncheol Kim	A massively scaleable decoder architecture for low-density parity-check codes.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Anand Selvarathinam, Euncheol Kim, Gwan Choi	Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels.	ICCD	2003	DBLP DOI BibTeX RDF	LDPC Decoder, Serial Architecture, Hardware Scaling, VLSI, Parallel Architecture, Fibre Channel
1	Byeong Min, Gwan Choi	ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation.	PRDC	2001	DBLP DOI BibTeX RDF
1	Zan Yang, Byeong Min, Gwan Choi	Simulation Using Code-Perturbation: Black- and White-Box Approach.	ISQED	2001	DBLP DOI BibTeX RDF
1	Zan Yang, Gwan Choi	An On-Line Testing Approach Using Code-Perturbation. (PDF / PS)	IOLTW	2001	DBLP DOI BibTeX RDF
1	Byeong Min, Gwan Choi	Verification Simulation Acceleration Using Code-Perturbation.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	code-perturbation, simulation, verification, coverage, fault
1	Zan Yang, Byeong Min, Gwan Choi	Si-emulation: system verification using simulation and emulation.	ITC	2000	DBLP DOI BibTeX RDF
1	Seung H. Hwang, Gwan S. Choi	A Reliability Testing Environment for Off-the-Shelf Memory Subsystems.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
1	Ronjeet Lal, Gwan S. Choi	Error and Failure Analysis of a UNIX Server. (PDF / PS)	HASE	1998	DBLP DOI BibTeX RDF
1	Seung H. Hwang, Gwan S. Choi	On-Chip Cache Memory Resilience. (PDF / PS)	HASE	1998	DBLP DOI BibTeX RDF
1	Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi	A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	transient fault injection, transient fault modeling, transient fault simulation, fault-tolerance, Single event upset
1	Gregory L. Ries, Gwan S. Choi, Ravishankar K. Iyer	Device-Level Transient Fault Modeling.	FTCS	1994	DBLP DOI BibTeX RDF
1	Gwan S. Choi, Ravishankar K. Iyer	Wear-Out Simulation Environment for VLSI Designs.	FTCS	1993	DBLP DOI BibTeX RDF
1	Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer	A Fast and Accurate Gate-Level Transient Fault Simulation Environment.	FTCS	1993	DBLP DOI BibTeX RDF
1	Gwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab	Fault behavior dictionary for simulation of device-level transients.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Gwan S. Choi, Ravishankar K. Iyer	FOCUS: An Experimental Environment for Fault Sensitivity Analysis.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF

Publications of Gwan Choi Gwan S. Choi ( http://dblp.L3S.de/Authors/Gwan_Choi )