Search results for "H.-S. Philip Wong"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra	Carbon Nanotube Robust Digital VLSI.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai	Metal-Oxide RRAM.	Proceedings of the IEEE	2012	DBLP DOI BibTeX RDF
1	Chen Chen, W. Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Dae Sung Lee, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chen Chen, W. Scott Lee, Roozbeh Parsa, Soogine Chong, J. Provine, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique.	DATE	2012	DBLP BibTeX RDF
1	Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra	Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Jason T. Ryan, Lan Wei, Jason P. Campbell, Ricki G. Southwick, Kin P. Cheung, Anthony S. Oates, H.-S. Philip Wong, John Suehle	Circuit-aware device reliability criteria methodology.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra	Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Saeroonter Oh, Jeongha Park, S. Simon Wong, H.-S. Philip Wong	Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design.	ISQED	2010	DBLP DOI BibTeX RDF
1	Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra	Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.	DAC	2010	DBLP DOI BibTeX RDF	CNT correlation, carbon nanotube, yield optimization, CNT
1	Shinobu Fujita, Shinichi Yasuda, Dae Sung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong	Detachable nano-carbon chip with ultra low power.	DAC	2010	DBLP DOI BibTeX RDF	NEMS, ultra-low power, 3D-IC
1	Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
1	Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra	Carbon nanotube circuits: Living with imperfections and variations.	DATE	2010	DBLP BibTeX RDF
1	Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra	Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.	DAC	2009	DBLP DOI BibTeX RDF	CNFET, carbon nanotube transistor, carbon nanotubes
1	SangBum Kim, Yuan Zhang, Byoungil Lee, Marissa Caldwell, H.-S. Philip Wong	Fabrication and Characterization of Emerging Nanoscale Memory.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Soogine Chong, Kerem Akarvardar, Roozbeh Parsa, Jun-Bo Yoon, Roger T. Howe, Subhasish Mitra, H.-S. Philip Wong	Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage.	ICCAD	2009	DBLP BibTeX RDF
1	Jie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong	Carbon nanotube transistor compact model for circuit design and performance optimization.	JETC	2008	DBLP DOI BibTeX RDF	VerilogA, carbon nanotube FET, compact model, CNT, HSPICE
1	Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra	Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong	Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI.	ISQED	2007	DBLP DOI BibTeX RDF
1	Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra	Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.	DAC	2007	DBLP DOI BibTeX RDF
1	H.-S. Philip Wong	Device and Technology Challenges for Nanoscale CMOS.	ISQED	2006	DBLP DOI BibTeX RDF
1	H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan	Carbon nanotube transistor circuits: models and tools for design and performance optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
1	H.-S. Philip Wong	Beyond the conventional transistor.	IBM Journal of Research and Development	2002	DBLP DOI BibTeX RDF
1	Yuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak	CMOS scaling into the 21st century: 0.1 µm and beyond.	IBM Journal of Research and Development	1995	DBLP BibTeX RDF

Publications of "H.-S. Philip Wong" ( http://dblp.L3S.de/Authors/H.-S._Philip_Wong )