| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hansu Cho, Samar Abdi |
Automatic generation of transducer models for multicore system design.  |
HLDVT  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinpeng Lv, Priyank Kalla, Florian Enescu |
Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Pellegrini, Valeria Bertacco |
Cardio: Adaptive CMPs for reliability through dynamic introspective operation. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Lisherness, Kwang-Ting (Tim) Cheng |
Coverage discounting: A generalized approach for testbench qualification. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Charlie Shucheng Zhu, Georg Weissenbacher, Divjyot Sethi, Sharad Malik |
SAT-based techniques for determining backbones for post-silicon fault localisation. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Banerjee, Tushar Gupta, Saurabh Jain |
A scalable hybrid verification system based on HDL slicing. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander W. Rath, Volkan Esen, Wolfgang Ecker |
Analog transaction level modeling. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Xie, Wolfgang Müller 0003, Florian Letombe |
IP-XACT based system level mutation testing. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Hu, Huy Nguyen, Michael S. Hsiao |
Sufficiency-based filtering of invariants for Sequential Equivalence Checking. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Charalambos Ioannides, Geoff Barrett, Kerstin Eder |
Introducing XCS to Coverage Directed test Generation. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Sara Vinco |
UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Sandeep K. Shukla (eds.) |
2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011 |
HLDVT |
2011 |
DBLP BibTeX RDF |
|
| 1 | Hans Eveking, Tobias Dornes, Martin Schweikert |
Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Karimibiuki, Kyle Balston, Alan J. Hu, André Ivanov |
Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bijan Alizadeh, Masahiro Fujita |
Modular equivalence verification of polynomial datapaths with multiple word-length operands. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Li, Kelson Gent, Michael S. Hsiao |
Utilizing GPGPUs for design validation with a modified Ant Colony Optimization. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Masoud Gharehbaghi, Masahiro Fujita |
Formal verification guided automatic design error diagnosis and correction of complex processors. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Matin Hashemi, Soheil Ghiasi |
Towards scalable utilization of embedded manycores in throughput-sensitive applications. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Frederic Risacher, Kenneth J. Schultz |
Software agnostic approaches to explore pre-silicon system performance. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik |
Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli |
Interactive presentation abstract: Assertion-based verification in embedded-software design. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mike Gemünde, Jens Brandt, Klaus Schneider |
Causality analysis of synchronous programs with refined clocks. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli |
Interactive presentation abstract: Reusing of properties after discretization of hybrid automata. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gunar Schirner |
Modeling, synthesis, and validation of heterogeneous biomedical embedded systems. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashvin Dsouza |
Static analysis of deadends in SVA constraints. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | John Sanguinetti, Eugene Zhang |
The relationship of code coverage metrics on high-level and RTL code. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Samar Abdi |
Automatic generation of host-compiled timed TLMs for high level design. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Satrajit Chatterjee, Michael Kishinevsky, Ümit Y. Ogras |
Quick formal modeling of communication fabrics to enable verification. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alper Sen, Magdy S. Abadir |
Coverage metrics for verification of concurrent SystemC designs using mutation testing. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | |
IEEE International High Level Design Validation and Test Workshop, HLDVT 2010, Anaheim, CA, USA, 10-12 June 2010 |
HLDVT |
2010 |
DBLP BibTeX RDF |
|
| 1 | Rajiv Bhatia, Eyal Bin, Eitan Marcus, Gil Shurek |
An ontology and constraint based approach to cache preloading. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | O. Sarbishei, Yu Pang, Katarzyna Radecka |
Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon |
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurizio Caramia, Michele Fabiano, Andrea Miele, Roberto Piazza, Paolo Prinetto |
Automated synthesis of EDACs for FLASH memories with user-selectable correction capability. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Stefano Soffia, Marco Roveri |
Semi-formal functional verification by EFSM traversing via NuSMV. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hoang M. Le, Daniel Große, Rolf Drechsler |
Towards analyzing functional coverage in SystemC TLM property checking. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Pranav Ashar |
Clock domain verification challenges and scalable solutions. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten |
Model reduction techniques for the formal verification of hardware dependent software. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumit Ahuja, Wei Zhang, Sandeep K. Shukla |
System level simulation guided approach to improve the efficacy of clock-gating. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rishiyur S. Nikhil |
ESL flows are enabled by high-level synthesis with universality. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicholas Donataccio, Hao Zheng |
An improvement in decomposed reachability analysis for symbolic model checking. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicola Bombieri, Giuseppe Di Guglielmo, Luigi Di Guglielmo, Michele Ferrari, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Alessandro Venturelli |
HIFSuite: Tools for HDL code conversion and manipulation. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Haiqiong Yao, Hao Zheng 0001, Chris J. Myers |
State space reductions for scalable verification of asynchronous designs. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yogesh S. Mahajan, Sharad Malik |
Utility of transaction-level hardware models in refinement checking. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wolfgang Müller 0003, Marcio F. da S. Oliveira, Henning Zabel, Markus Becker |
Verification of real-time properties for Hardware-dependent Software. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Gao, Kwang-Ting Cheng |
A case study of Time-Multiplexed Assertion Checking for post-silicon debugging. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri |
Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker |
Fast and accurate UML State Chart modeling using TLM+ control flow abstraction. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bart Vermeulen, Kees Goossens |
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Weiwei Chen, Xu Han, Rainer Dömer |
ESL design and multi-core validation using the System-on-Chip Environment. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianpiero Cabodi, Leandro Dipietro, Marco Murciano, Sergio Nocco |
Exploiting incrementality in SAT-based search for multiple equivalence-preserving transformations in combinational circuits. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Susmit Jha, Wenchao Li, Sanjit A. Seshia |
Localizing transient faults using dynamic bayesian networks. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara |
RTL DFT techniques to enhance defect coverage for functional test sequences. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Debapriya Chatterjee, Valeria Bertacco |
Activity-based refinement for abstraction-guided simulation. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurizio Caramia, Stefano Di Carlo, Michele Fabiano, Paolo Prinetto |
FLARE: A design environment for FLASH-based space applications. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Lingyi Liu, Shobha Vasudevan |
STAR: Generating input vectors for design validation by static analysis of RTL. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bijan Alizadeh, Masahiro Fujita |
Modular arithmetic decision procedure with auto-correction mechanism. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ziyad Hanna, Thomas F. Melham |
A symbolic execution framework for algorithm-level modelling. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | |
IEEE International High Level Design Validation and Test Workshop, HLDVT 2009, San Francisco, CA, USA, 4-6 November 2009 |
HLDVT |
2009 |
DBLP BibTeX RDF |
|
| 1 | Miroslav N. Velev, Ping Gao 0002 |
Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | In-Ho Moon, Kevin Harer |
Learning from constraints for formal property checking. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Huan Chen 0001, João Marques-Silva |
TG-PRO: A new model for SAT-based ATPG. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer |
Dynamic verification of Multicore Communication applications in MCAPI. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bin Xue, Sandeep K. Shukla |
Analysis of scheduled Latency insensitive systems with periodic clock calculus. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sung-Boem Park, Subhasish Mitra |
IFRA: Post-silicon bug localization in processors. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Zheng |
A coordinated reachability analysis method for modular verification of asynchronous designs. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maheshwar Chandrasekar, Michael S. Hsiao |
Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Ahuja, S. Shukla |
MCBCG: Model Checking Based Sequential Clock-Gating. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Andreas G. Veneris |
Automated debugging with high level abstraction and refinement. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunil R. Shenoy |
Leadership Microprocessors: Validation, debug and test. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Zeljko Zilic |
A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Lisherness, Kwang-Ting Cheng |
An instrumented observability coverage method for system validation. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | J. Hao, Valeria Bertacco |
PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Sunil P. Khatri |
Fault table generation using Graphics Processing Units. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason G. Tong, Marc Boule, Zeljko Zilic |
Airwolf-TG: A test generator for assertion-based dynamic verification. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicola Nicolici, Ho Fai Ko |
Design-for-debug for post-silicon validation: Can high-level descriptions help? |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Prabhat Mishra |
Chairs' welcome message. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sven Verdoolaege, Martin Palkovic, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor |
Experience with widening based equivalence checking in realistic multimedia systems. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia |
Hardware Trojan: Threats and emerging solutions. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
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