| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Li Li, Yinghai Lu, Hai Zhou |
Optimal prescribed-domain clock skew scheduling.  |
ASP-DAC  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuankai Chen, Hai Zhou |
Buffer minimization in pipelined SDF scheduling on multi-core platforms. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rong Ye, Feng Yuan, Hai Zhou, Qiang Xu |
Clock skew scheduling for timing speculation. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Hai Zhou, Kevin Sparks, Nandu Gopalakrishnan, Pantelis Monogioudis, Francis Dominique, Peter Busschbach, Jim Seymour |
Deprioritization of heavy users in wireless networks. |
IEEE Communications Magazine |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kurt Keutzer, Peng Li, Li Shang, Hai Zhou |
A Special Section on Multicore Parallel CAD: Algorithm Design and Programming. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou |
MSV-Driven Floorplanning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng |
Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng |
Binning Optimization for Transparently-Latched Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack |
FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Li, Yinghai Lu, Hai Zhou |
Optimal multi-domain clock skew scheduling. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Sun 0005, Yinghai Lu, Hai Zhou, Xuan Zeng |
Post-routing layer assignment for double patterning. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanling Zhi, Hai Zhou, Xuan Zeng |
A practical method for multi-domain clock skew optimization. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng |
Parallel cross-layer optimization of high-level synthesis and physical design. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Li, Jian Sun 0005, Yinghai Lu, Hai Zhou, Xuan Zeng |
Low power discrete voltage assignment under clock skew scheduling. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuankai Chen, Hai Zhou, Robert P. Dick |
Integrated circuit white space redistribution for temperature optimization. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng |
An efficient algorithm for multi-domain clock skew scheduling. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng |
Multicore Parallelization of Min-Cost Flow for CAD Applications. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou |
Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang |
Hybrid energy storage system integration for vehicles. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
electric-drive vehicles, energy storage systems, analysis |
| 1 | Debasish Das, Jia Wang, Hai Zhou |
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kurt Keutzer, Peng Li, Li Shang, Hai Zhou |
ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Wang, Debasish Das, Hai Zhou |
Gate Sizing by Lagrangian Relaxation Revisited. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail |
A Timing-Dependent Power Estimation Framework Considering Coupling. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | T. Izumi, Hai Zhou, Zuowei Li |
Optimal Design of Gear Ratios and Offset for Energy Conservation of an Articulated Manipulator. |
IEEE T. Automation Science and Engineering |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Debasish Das, William Scott, Shahin Nazarian, Hai Zhou |
An efficient current-based logic cell model for crosstalk delay analysis. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou |
Retiming and resynthesis with sweep are complete for sequential transformation. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yao Zhao, Sagar Vemuri, Jiazhen Chen, Yan Chen, Hai Zhou, Zhi Fu |
Exception triggered DoS attacks on wireless networks. |
DSN |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng |
Multicore parallel min-cost flow algorithm for CAD applications. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
min-cost flow, parallel programming, multicore |
| 1 | Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng |
Provably good and practically efficient algorithms for CMP dummy fill. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
covering linear programming, dummy fill problem, design for manufacturability |
| 1 | Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng |
Statistical reliability analysis under process variation and aging effects. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
process variations, yield, NBTI |
| 1 | Jia Wang, Hai Zhou |
Risk aversion min-period retiming under process variations. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Wang, Hai Zhou |
Exploring adjacency in floorplanning. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee |
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Gong, Hai Zhou, Jun Tao, Xuan Zeng |
Binning optimization based on SSTA for transparently-latched circuits. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Hai Zhou |
A new efficient retiming algorithm derived by formal manipulation. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Clockperiod minimization, algorithm derivation, retiming |
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou |
Optimizing wirelength and routability by searching alternative packings in floorplanning. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
wirelength reduction, Floorplanning |
| 1 | Jieyi Long, Hai Zhou, Seda Ogrenci Memik |
EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruiming Chen, Hai Zhou |
Fast Estimation of Timing Yield Bounds for Process Variations. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou |
Circuit Retiming. |
Encyclopedia of Algorithms |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou |
Rectilinear Steiner Tree. |
Encyclopedia of Algorithms |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou |
Rectilinear Spanning Tree. |
Encyclopedia of Algorithms |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou |
Circuit Retiming: An Incremental Approach. |
Encyclopedia of Algorithms |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos D. Liveris, Hai Zhou, Robert P. Dick, Prithviraj Banerjee |
State space abstraction for parameterized self-stabilizing embedded systems. |
EMSOFT |
2008 |
DBLP DOI BibTeX RDF |
verification, abstraction, parameterized systems, self-stabilizing systems, network invariants |
| 1 | Jieyi Long, Hai Zhou, Seda Ogrenci Memik |
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
minimum terminal spanning tree, spanning graph, routing, physical design, steiner tree |
| 1 | Jia Wang, Hai Zhou |
An efficient incremental algorithm for min-area retiming. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
retiming |
| 1 | Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou |
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee |
A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Wang, Hai Zhou |
Linear constraint graph for floorplan optimization with soft blocks. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruiming Chen, Hai Zhou |
An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Hai Zhou, Narendra V. Shenoy |
Advances in Computation of the Maximum of a Set of Gaussian Random Variables. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou |
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Lin, Hai Zhou |
Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou |
Unified Incremental Physical-Level and High-Level Synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Wang, Hai Zhou |
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud (eds.) |
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007 |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP BibTeX RDF |
|
| 1 | Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack |
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
modeling, crosstalk, static timing analysis |
| 1 | Jia Wang, Ming-Yang Kao, Hai Zhou |
Address generation for nanowire decoders. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
testing, decoder, nanowire |
| 1 | Ruiming Chen, Hai Zhou |
Fast Min-Cost Buffer Insertion under Process Variations. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruiming Chen, Hai Zhou |
Fast Buffer Insertion for Yield Optimization Under Process Variations. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee |
Retiming for Synchronous Data Flow Graphs. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
cycle length, synchronous data flow graphs, retiming |
| 1 | Chuan Lin, Hai Zhou |
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
delay padding, prescribed skew domains, optimal skew scheduling algorithm, domain assignment, sequential circuit, flip-flops, memory elements, clock period, clock skew scheduling |
| 1 | Ruiming Chen, Hai Zhou |
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou |
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Lin, Aiguo Xie, Hai Zhou |
Design closure driven delay relaxation based on convex cost network flow. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruiming Chen, Hai Zhou |
Timing budgeting under arbitrary process variations. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Wang, Debasish Das, Hai Zhou |
Gate sizing by Lagrangian relaxation revisited. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou |
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Hai Zhou |
Gate-size optimization under timing constraints for coupling-noise reduction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruiming Chen, Hai Zhou |
Statistical timing verification for transparently latched circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruiming Chen, Hai Zhou |
An Efficient Data Structure for Maxplus Merge in Dynamic Programming. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Lin, Hai Zhou |
Optimal wire retiming without binary search. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Hai Zhou |
Statistical Timing Analysis With Coupling. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Narendra V. Shenoy, Hai Zhou |
Statistical Timing Yield Optimization by Gate Sizing. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Lin, Jia Wang, Hai Zhou |
Clustering for Processing Rate Optimization. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Wang, Hai Zhou, Ping-Chih Wu |
Processing Rate Optimization by Sequential System Floorplanning. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Hai Zhou, Narendra V. Shenoy |
Advances in Computation of the Maximum of a Set of Random Variables. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou (eds.) |
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP BibTeX RDF |
|
| 1 | Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou |
Yield-Aware Cache Architectures. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Wang, Hai Zhou |
Optimal jumper insertion for antenna avoidance under ratio upper-bound. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
jumper insertion, antenna effect |
| 1 | Chuan Lin, Hai Zhou |
An efficient retiming algorithm under setup and hold constraints. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
retiming |
| 1 | Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou |
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Lin, Hai Zhou, Chris C. N. Chu |
A revisit to floorplan optimization by Lagrangian relaxation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
floorplan, Lagrangian relaxation |
| 1 | Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou |
A timing dependent power estimation framework considering coupling. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack |
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang |
Spanning graph-based nonrectilinear steiner tree algorithms. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Lin, Hai Zhou |
Wire retiming as fixpoint computation. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee |
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee |
Leakage power optimization with dual-Vth library in high-level synthesis. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
dual-Vth, optimization, high-level synthesis, leakage power |
| 1 | Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou |
Incremental exploration of the combined physical and behavioral design space. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
high-level synthesis, floorplan, incremental |
| 1 | Jia Wang, Hai Zhou |
Interconnect estimation without packing via ACG floorplans. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Hai Zhou |
Yield driven gate sizing for coupling-noise reduction under uncertainty. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou |
Deriving a new efficient algorithm for min-period retiming. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Pan, Chris C. N. Chu, Hai Zhou |
Timing yield estimation using statistical static timing analysis. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, Hai Zhou |
A unified framework for statistical timing analysis with coupling and multiple input switching. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Chuan Lin, Jia Wang, Hai Zhou |
Clustering for processing rate optimization. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Ruiming Chen, Hai Zhou |
Efficient algorithms for buffer insertion in general circuits based on network flow. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Chuan Lin, Hai Zhou |
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Debjit Sinha, Narendra V. Shenoy, Hai Zhou |
Statistical gate sizing for timing yield optimization. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Hai Zhou |
Efficient Steiner tree construction based on spanning graphs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou, Chuan Lin |
Retiming for wire pipelining in system-on-chip. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
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