Search results for "Hamid Mahmoodi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Roberto Menchaca, Hamid Mahmoodi	Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS.	ISQED	2012	DBLP DOI BibTeX RDF
1	Shreyas Kumar Krishnappa, Hamid Mahmoodi	Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology.	ISQED	2011	DBLP DOI BibTeX RDF
1	Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy	Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology.	ICCD	2011	DBLP DOI BibTeX RDF
1	Vish Ganti, Hamid Mahmoodi	Comparative analysis of copper and CNT interconnects for H-tree clock distribution.	ICCD	2011	DBLP DOI BibTeX RDF
1	Vikram G. Rao, Hamid Mahmoodi	Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology.	ICCD	2011	DBLP DOI BibTeX RDF
1	Somnath Paul, Hamid Mahmoodi, Swarup Bhunia	Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy	Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Minki Cho, Jason Schlessman, Hamid Mahmoodi, Marilyn Wolf, Saibal Mukhopadhyay	Postsilicon Adaptation for Low-Power SRAM under Process Variation.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yngvar Berg, Tuan Vu Cao	New SRAM design using body bias technique for ultra low power applications.	ISQED	2010	DBLP DOI BibTeX RDF
1	Anuj Pushkarna, Hamid Mahmoodi	Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, aging, SRAM, power gating
1	Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy	Data-dependant sense-amplifier flip-flop for low power applications.	CICC	2010	DBLP DOI BibTeX RDF
1	Ankitchandra Shah, Hamid Mahmoodi	Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits.	SoCC	2010	DBLP DOI BibTeX RDF
1	Anuj Pushkarna, Sajna Raghavan, Hamid Mahmoodi	Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies.	SoCC	2010	DBLP DOI BibTeX RDF
1	Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy	Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao	New subthreshold concepts in 65nm CMOS technology.	ISQED	2009	DBLP DOI BibTeX RDF
1	Hamid Mahmoodi, Ali A. Jalali	Virtual Age: Enabling Technologies and Trends.	ITNG	2009	DBLP DOI BibTeX RDF	Virtual age, fourth wave, internet, information technology
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Snorre Aunet, Tuan Vu Cao, Ali Peiravi	Ultra Low Power Full Adder Topologies.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Tuan Vu Cao	Improved write margin 6T-SRAM for low supply voltage applications.	SoCC	2009	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy	Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
1	Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao	65NM sub-threshold 11T-SRAM for ultra low voltage applications.	SoCC	2008	DBLP DOI BibTeX RDF
1	Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy	Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Rajani Kuchipudi, Hamid Mahmoodi	Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS.	ISQED	2007	DBLP DOI BibTeX RDF
1	Keejong Kim, Hamid Mahmoodi, Kaushik Roy	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
1	Vishwanadh Tirumalashetty, Hamid Mahmoodi	Clock Gating and Negative Edge Triggering for Energy Recovery Clock.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia	Low-overhead design technique for calibration of maximum frequency at multiple operating points.	ICCAD	2007	DBLP DOI BibTeX RDF	frequency calibration, voltage sensitivity, dynamic voltage and frequency scaling, ring oscillator
1	Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy	A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici	Double-Gate SOI Devices for Low-Power and High-Performance Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia	Low power synthesis of dynamic logic circuits using fine-grained clock gating.	DATE	2006	DBLP DOI BibTeX RDF
1	Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy	A leakage control system for thermal stability during burn-in test.	ITC	2005	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy	Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring.	ITC	2005	DBLP DOI BibTeX RDF
1	Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy	Process Variation Tolerant Online Current Monitor for Robust Systems.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy	Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy	Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy	A process-tolerant cache architecture for improved yield in nanoscale technologies.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy	Low-power scan design using first-level supply gating.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy	Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET.	ISQED	2005	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy	Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi	A high speed and leakage-tolerant domino logic for high fan-in gates.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high speed, noise immunity, deep submicron, fan-in, domino
1	Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy	Energy recovery clocked dynamic logic.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	logic, clock, domino, energy recovery
1	Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy	A novel synthesis approach for active leakage power reduction using dynamic supply gating.	DAC	2005	DBLP DOI BibTeX RDF
1	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy	Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.	VTS	2005	DBLP DOI BibTeX RDF	Failure mechanixm, Process Variation, DFT, SRAM, March Test
1	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.	DATE	2005	DBLP DOI BibTeX RDF
1	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Pre-capturing static pulsed flip-flops.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici	Double-gate SOI devices for low-power and high-performance applications.	ICCAD	2005	DBLP BibTeX RDF
1	Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.	ICCD	2005	DBLP DOI BibTeX RDF
1	Hamid Mahmoodi-Meimand, Kaushik Roy	Data-retention flip-flops for power-down applications.	ISCAS	2004	DBLP BibTeX RDF
1	Hamid Mahmoodi-Meimand, Kaushik Roy	Dual-edge triggered level converting flip-flops.	ISCAS	2004	DBLP BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.	DFT	2004	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy	Statistical design and optimization of SRAM cell for yield enhancement.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy	A Novel Low-Power Scan Design Technique Using Supply Gating.	ICCD	2004	DBLP DOI BibTeX RDF
1	Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy	Energy recovery clocking scheme and flip-flops for ultra low-energy applications.	ISLPED	2003	DBLP DOI BibTeX RDF	flip-flop, clock, clock tree, energy recovery, adiabatic
1	Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand	Leakage Current in Deep-Submicron CMOS Circuits.	Journal of Circuits, Systems, and Computers	2002	DBLP DOI BibTeX RDF
1	Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy	High performance and low power FIR filter design based on sharing multiplication.	ISLPED	2002	DBLP DOI BibTeX RDF	FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder
1	Hamid Mahmoodi-Meimand, Ali Afzali-Kusha	Efficient power clock generation for adiabatic logic.	ISCAS	2001	DBLP DOI BibTeX RDF

Publications of Hamid Mahmoodi Hamid Mahmoodi-Meimand ( http://dblp.L3S.de/Authors/Hamid_Mahmoodi )