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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 28 occurrences of 25 keywords
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Results
Found 20 publication records. Showing 20 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jurriaan Kamer, Harald P. E. Vranken |
The Impact of Server Virtualization on ITIL Processes.  |
CLOSER  |
2011 |
DBLP BibTeX RDF |
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| 1 | Harald P. E. Vranken, Jens Haag, Tobias Horsmann, Stefan Karsch |
A Distributed Virtual Computer Security Lab.  |
CSEDU  |
2011 |
DBLP BibTeX RDF |
|
| 1 | Herman Koppelman, Harald P. E. Vranken |
Experiences with a synchronous virtual classroom in distance education.  |
ITiCSE  |
2008 |
DBLP DOI BibTeX RDF |
active learning, pedagogy, distance education, educational technology, virtual classroom |
| 1 | Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke |
Fault detection and diagnosis with parity trees for space compaction of test responses.  |
DAC  |
2006 |
DBLP DOI BibTeX RDF |
fault diagnosis, fault detection, test data compression |
| 1 | Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers |
Efficient Pattern Mapping for Deterministic Logic BIST.  |
ITC  |
2004 |
DBLP DOI BibTeX RDF |
BDDs, Logic BIST |
| 1 | Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker |
X-Masking During Logic BIST and Its Impact on Defect Coverage.  |
ITC  |
2004 |
DBLP DOI BibTeX RDF |
X-Masking, Resistive Bridging Faults, Defect Coverage, Logic BIST |
| 1 | Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich |
Impact of Test Point Insertion on Silicon Area and Timing during Layout.  |
DATE  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Harald P. E. Vranken, Friedrich Hapke, Soenke Rogge, Domenico Chindamo, Erik H. Volkerink |
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume.  |
ITC  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier |
Enhanced Reduced Pin-Count Test for Full-Scan Design.  |
J. Electronic Testing  |
2002 |
DBLP DOI BibTeX RDF |
reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test |
| 1 | Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich |
Application of Deterministic Logic BIST on Industrial Circuits.  |
J. Electronic Testing  |
2001 |
DBLP DOI BibTeX RDF |
industrial applications, scan-based BIST, logic BIST |
| 1 | Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier |
Enhanced reduced pin-count test for full-scan design.  |
ITC  |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | A. Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich |
Circuit partitioning for efficient logic BIST synthesis.  |
DATE  |
2001 |
DBLP DOI BibTeX RDF |
divide-and-conquer, circuit partitioning, deterministic BIST |
| 1 | Harald P. E. Vranken |
Debug Facilities in the TriMedia CPU64 Architecture.  |
J. Electronic Testing  |
2000 |
DBLP DOI BibTeX RDF |
application debug, VLIW processor, design-for-debug |
| 1 | Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen |
Application of deterministic logic BIST on industrial circuits.  |
ITC  |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Harald P. E. Vranken, Tomás Garciá Garciá, Sjouke Mauw, Loe M. G. Feijs |
IC Design Validation Using Message Sequence Charts. (PDF / PS)  |
EUROMICRO  |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Jeroen Voeten, Harald P. E. Vranken |
Behavior-Preserving Transformations for Design-for-Test.  |
EUROMICRO  |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel |
TriMedia CPU64 Architecture.  |
ICCD  |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers |
Design-For-Debug in Hardware/Software Co-Design.  |
CODES  |
1997 |
DBLP DOI BibTeX RDF |
system integration and test, hardware/software co-design, design validation, design-for-debug |
| 1 | Harald P. E. Vranken, Marc F. Witteman, Ronald C. van Wuijtswinkel |
Design for Testability in Hardware-Software Systems.  |
IEEE Design & Test of Computers  |
1996 |
DBLP DOI BibTeX RDF |
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| 1 | Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers, J. H. M. M. van Rhee |
System-Level Testability of Hardware/Software Systems.  |
ITC  |
1994 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #20 of 20 (100 per page; Change: )
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