Search results for "Hardware Speculation"

Found 7 publication records. Showing 7 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Walter Yuan-Hwa Li, Chin-Ling Huang, Chung-Ping Chung	Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity.	ICPP	2011	DBLP DOI BibTeX RDF	Execute Ahead, Hardware Speculation, Instruction-Level Parallelism, Processor Architecture, Memory-Level Parallelism, Runahead Execution
1	Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay	Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism
1	Craig B. Zilles, Naveen Neelakantam	Reactive Techniques for Controlling Software Speculation.	CGO	2005	DBLP DOI BibTeX RDF
1	Stevan A. Vlaovic, Edward S. Davidson	Boosting trace cache performance with nonhead miss speculation.	ICS	2002	DBLP DOI BibTeX RDF	optimization, branch prediction, trace cache, x86
1	Matthew C. Merten, Andrew R. Trick, Ronald D. Barnes, Erik M. Nystrom, Christopher N. George, John C. Gyllenhaal, Wen-mei W. Hwu	An Architectural Framework for Runtime Optimization.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Postlink optimization, hardware profiling, low-overhead profiling, program hot spot, partial function inlining, trace formation and optimization, dynamic optimization, runtime optimization, code layout
1	Chris Gniady, Babak Falsafi, T. N. Vijaykumar	Is SC + ILP=RC?	ISCA	1999	DBLP DOI BibTeX RDF
1	Zhiyuan Li, Jenn-Yuan Tsai, Xin Wang, Pen-Chung Yew, Bess Zheng	Compiler Techniques for Concurrent Multithreading with Hardware Speculation Support.	LCPC	1996	DBLP DOI BibTeX RDF

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