Search results for "Hardware acceleration"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	David Szczesny, Sebastian Hessel, Felix Bruns, Attila Bilgic	On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	embedded systems, real-time, hardware acceleration, virtual prototyping, hardware/software co-design, LTE, DMA
2	Tse-Wei Chen, Yi-Ling Chen, Shao-Yi Chien	Photo Retrieval Based on Spatial Layout with Hardware Acceleration for Mobile Devices.	IEEE Trans. Mob. Comput.	2011	DBLP DOI BibTeX RDF	parallel processing, image segmentation, hardware acceleration, K-Means clustering, Photo retrieval
2	Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh	Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Thomas Lenart, Mats Gustafsson, Viktor Öwall	A Hardware Acceleration Platform for Digital Holographic Imaging.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	digital holography, flexible FFT, data scaling, hybrid floating-point, burst oriented memory, matrix transpose
2	Stephen L. Smith, Andrew J. Greensted, Jon Timmis	Hardware Acceleration of an Immune Network Inspired Evolutionary Algorithm for Medical Diagnosis.	ICES	2008	DBLP DOI BibTeX RDF	Parkinson’s disease, Evolutionary algorithm, Artificial immune systems, Hardware acceleration, Immune networks
2	Dionisis Chaikalis, Georgios Passalis, Nikos Sgouros, Dimitris Maroulis, Theoharis Theoharis	Hardware Acceleration for 3D Image Reconstruction.	Panhellenic Conference on Informatics	2008	DBLP DOI BibTeX RDF
2	Holger Scherl, Stefan Hoppe, Markus Kowarschik, Joachim Hornegger	Design and implementation of the software architecture for a 3-D reconstruction system in medical imaging.	ICSE	2008	DBLP DOI BibTeX RDF	hardware abstraction layer, software design and architecture, parallel programming, patterns, medical imaging, hardware acceleration, 3-d reconstruction
2	Qinru Qiu, Daniel J. Burns, Prakash Mukre, Qing Wu	Hardware acceleration of multi-deme genetic algorithm for the application of DNA codeword searching.	GECCO	2007	DBLP DOI BibTeX RDF	genetic algorithm, hardware acceleration, DNA
2	H. Andrés Lagar-Cavilla, Niraj Tolia, Mahadev Satyanarayanan, Eyal de Lara	VMM-independent graphics acceleration.	VEE	2007	DBLP DOI BibTeX RDF	VMM-independence, virtualization, graphics, portability, hardware acceleration
2	Bruno Zatt, Valter Ferreira, Luciano Volcan Agostini, Flávio Rech Wagner, Altamiro Amadeu Susin, Sergio Bampi	Motion Compensation Hardware Accelerator Architecture for H.264/AVC.	PSIVT	2007	DBLP DOI BibTeX RDF	MPEG-4 AVC, Video Coding, H.264/AVC, Motion Compensation, Hardware Acceleration
2	David J. Lau, Orion Pritchard	Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions.	FPL	2006	DBLP DOI BibTeX RDF
2	Stephan Gatzka, Christian Hochberger	On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices.	HICSS	2005	DBLP DOI BibTeX RDF
2	Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk	Hardware Acceleration of Hidden Markov Model Decoding for Person Detection.	DATE	2005	DBLP DOI BibTeX RDF
2	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Power emulation: a new paradigm for power estimation.	DAC	2005	DBLP DOI BibTeX RDF	simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels
2	Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung	Communication-efficient hardware acceleration for fast functional simulation.	DAC	2004	DBLP DOI BibTeX RDF	functional verification, communication overhead, simulation acceleration
2	Chengyu Sun, Divyakant Agrawal, Amr El Abbadi	Hardware Acceleration for Spatial Selections and Joins.	SIGMOD Conference	2003	DBLP DOI BibTeX RDF	spatial selection, hardware acceleration, spatial join
2	Srihari Cadambi, Chandra Mulpuri, Pranav Ashar	A fast, inexpensive and scalable hardware acceleration technique for functional simulation.	DAC	2002	DBLP DOI BibTeX RDF	FPGA, hardware acceleration, VLIW, functional simulation
2	M. Ernst, Michael Jung, Felix Madlener, Sorin A. Huss, Rainer Blümel	A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n).	CHES	2002	DBLP BibTeX RDF	$ mathbb {GF}(2^n)$ arithmetic, Karatsuba multiplication, VHDL model generator, coprocessor synthesis, FPGA hardware acceleration, Atmel FPSLIC platform, Elliptic Curve cryptography
2	Lisa M. Sobierajski, Ricardo S. Avila	A Hardware Acceleration Method for Volumetric Ray Tracing.	IEEE Visualization	1995	DBLP DOI BibTeX RDF	Volume Rendering, Ray Tracing, Hardware Acceleration
2	Philip M. Spira, Carl Hage	Hardware acceleration of gate array layout.	DAC	1985	DBLP DOI BibTeX RDF
1	Tobias Welp, Nathan Kitchen, Andreas Kuehlmann	Hardware Acceleration for Constraint Solving for Random Simulation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Chen Liu, Omar Granados, Rolando Duarte, Jean Andrian	Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components.	JIPS	2012	DBLP DOI BibTeX RDF
1	Agathoklis Papadopoulos, Vasilis J. Promponas, Theocharis Theocharides	Towards systolic hardware acceleration for local complexity analysis of massive genomic data.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Michael Gilroy, James Irvine, Robert Atkinson	RAID 6 Hardware Acceleration.	ACM Trans. Embedded Comput. Syst.	2011	DBLP DOI BibTeX RDF
1	Hyungwook Park, Paul A. Fishwick	An analysis of queuing network simulation using GPU-based hardware acceleration.	ACM Trans. Model. Comput. Simul.	2011	DBLP DOI BibTeX RDF
1	Weihang Zhu	Massively parallel differential evolution - pattern search optimization with graphics hardware acceleration: an investigation on bound constrained optimization problems.	J. Global Optimization	2011	DBLP DOI BibTeX RDF
1	Jed Kao-Tung Chang, Chen Liu, Shaoshan Liu, Jean-Luc Gaudiot	Workload characterization of cryptography algorithms for hardware acceleration (abstracts only).	SIGMETRICS Performance Evaluation Review	2011	DBLP DOI BibTeX RDF
1	Jung Kuk Kim, Zhengya Zhang, Jeffrey A. Fessler	Hardware acceleration of iterative image reconstruction for X-ray computed tomography.	ICASSP	2011	DBLP DOI BibTeX RDF
1	Qiwei Jin, Wayne Luk, David B. Thomas	Unifying Finite Difference Option-Pricing for Hardware Acceleration.	FPL	2011	DBLP DOI BibTeX RDF	FPGA, Framework, Finance, Finite Difference, Option Pricing
1	David Fuschelberger, Ioannis Pyrounakis, Tasos Dagiuklas, Nikolaos S. Voros, Carlos Ribeiro	Next Generation Smart Home Systems Using Hardware Acceleration Techniques.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Felipe Montoya-Franco, Andrés F. Serna-Morales, Flavio Prieto	3D Object Modeling with Graphics Hardware Acceleration and Unsupervised Neural Networks.	ISVC	2011	DBLP DOI BibTeX RDF
1	Jared Casper, Tayo Oguntebi, Sungpack Hong, Nathan Grasso Bronson, Christos Kozyrakis, Kunle Olukotun	Hardware acceleration of transactional memory on commodity systems.	ASPLOS	2011	DBLP DOI BibTeX RDF
1	Xiaotao Chang, Yike Ma, Hubertus Franke, Kun Wang, Rui Hou, Hao Yu, Terry Nelms	Optimization of stateful hardware acceleration in hybrid architectures.	DATE	2011	DBLP BibTeX RDF
1	Michel Voyer, Sylvain-Robert Rivard, Luc Morin, Hung Tien Bui	Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Paulo Da Cunha Possa, David Schaillie, Carlos Valderrama	FPGA-based hardware acceleration: A CPU/accelerator interface exploration.	ICECS	2011	DBLP DOI BibTeX RDF
1	Jed Kao-Tung Chang, Chen Liu, Shaoshan Liu, Jean-Luc Gaudiot	Workload Characterization of Cryptography Algorithms for Hardware Acceleration.	ICPE	2011	DBLP DOI BibTeX RDF
1	Imre Pechan, Béla Féher	Molecular Docking on FPGA and GPU Platforms.	FPL	2011	DBLP DOI BibTeX RDF	FPGA vs, AutoDock, bioinformatics, GPU, hardware acceleration, molecular docking
1	Steven Derrien, Patrice Quinton	Hardware Acceleration of HMMER on FPGAs.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Christopher Claus, Walter Stechele	AutoVision - Reconfigurable Hardware Acceleration for Video-Based Driver Assistance.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
1	Jed Kao-Tung Chang, Shaoshan Liu, Jean-Luc Gaudiot, Chen Liu	The Performance Analysis and Hardware Acceleration of Crypto-computations for Enhanced Security.	PRDC	2010	DBLP DOI BibTeX RDF
1	Gerald Hempel, Christian Hochberger, Andreas Koch	A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor.	FPL	2010	DBLP DOI BibTeX RDF
1	Maxwell Walton, Gary William Grewal, Gerarda Darlington	Hardware acceleration of Scatter Search.	HPCS	2010	DBLP DOI BibTeX RDF
1	Tomás Martínek, Matej Lexa	Hardware Acceleration of Approximate Tandem Repeat Detection.	FCCM	2010	DBLP DOI BibTeX RDF
1	Soumya Maity, Padmalochan Bera, Soumya Kanti Ghosh	A mobile IP based WLAN security management framework with reconfigurable hardware acceleration.	SIN	2010	DBLP DOI BibTeX RDF
1	Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar	FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	René Müller, Jens Teubner	FPGAs: a new point in the database design space.	EDBT	2010	DBLP DOI BibTeX RDF	FPGA, VLSI, hardware acceleration, data processing
1	Maxwell Walton, Gary Gréwal, Gerarda Darlington	Parallel FPGA-based implementation of scatter search.	GECCO	2010	DBLP DOI BibTeX RDF	0-1 knapsack problem, field programmable gate arrays, pipelining, hardware acceleration, data parallelism, scatter search
1	Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman	Network-on-Chip Hardware Accelerators for Biological Sequence Alignment.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	DNA/protein sequence alignment, on-chip parallelism, bioinformatics, Network-on-chip, hardware acceleration
1	Ramin Mafi, Shahin Sirouspour, Behzad Mahdavikhah, Brian Moody, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici	A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies.	IEEE T. Haptics	2010	DBLP DOI BibTeX RDF	Object deformation, FPGA, parallel computing, haptics, finite element method, hardware acceleration, real-time simulation
1	Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steven Swanson, Michael Bedford Taylor	Conservation cores: reducing the energy of mature computations.	ASPLOS	2010	DBLP DOI BibTeX RDF	conservation core, heterogeneous many-core, utilization wall, patching
1	Adam B. Kinsman, Nicola Nicolici	Robust design methods for hardware accelerators for iterative algorithms in scientific computing.	DAC	2010	DBLP DOI BibTeX RDF	bit-width allocation, satisfiability-modulo theory
1	Jing Yan, Ning-Yi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-Hsiung Hsu	LambdaRank acceleration for relevance ranking in web search engines (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	lambdarank algorithms
1	Isidoros Sideris, Nikos K. Moshopoulos, Kiamal Z. Pekmestzi	A hardware peripheral for Java bytecodes translation acceleration.	SAC	2010	DBLP DOI BibTeX RDF	stack folding, ASIC, RISC, Java processor
1	Shimin Chen, Michael Kozuch, Phillip B. Gibbons, Michael P. Ryan, Theodoros Strigkos, Todd C. Mowry, Olatunji Ruwase, Evangelos Vlachos, Babak Falsafi, Vijaya Ramachandran	Flexible Hardware Acceleration for Instruction-Grain Lifeguards.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas	FPGA-based hardware acceleration for Boolean satisfiability.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Boolean satisfiabilty (SAT), boolean constant propagation (BCP), conflict induced clauses, non-chronological backtrack, FPGA
1	Sebastian Fischmeister, Robert Trausmuth, Insup Lee	Hardware Acceleration for Programmable Real-Time Ethernet.	IEEE Trans. Industrial Informatics	2009	DBLP DOI BibTeX RDF
1	Byeong Kil Lee, Lizy K. John	Hardware Acceleration for Media/Transaction Applications in Network Processors.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Jason Cong, Yi Zou	FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation.	TRETS	2009	DBLP DOI BibTeX RDF
1	Weihang Zhu, James Curry	Parallel Ant Colony with Local Pattern Search for Nonlinear Function Optimization with Graphics Hardware Acceleration.	SMC	2009	DBLP DOI BibTeX RDF
1	David W. Thöni, Alfred Strey	Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithm.	FPL	2009	DBLP DOI BibTeX RDF
1	José A. Joao, Onur Mutlu, Yale N. Patt	Flexible reference-counting-based hardware acceleration for garbage collection.	ISCA	2009	DBLP DOI BibTeX RDF	garbage collection, reference counting
1	Hritam Dutta, Frank Hannig, Jürgen Teich	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.	ARCS	2009	DBLP DOI BibTeX RDF
1	Junguk Cho, Bridget Benson, Ryan Kastner	Hardware acceleration of multi-view face detection.	SASP	2009	DBLP DOI BibTeX RDF
1	Gregory B. Newby	Hardware acceleration prospects and challenges for high performance computing.	AICCSA	2009	DBLP DOI BibTeX RDF
1	Peter Bertels, Wim Heirman, Dirk Stroobandt	Strategies for dynamic memory allocation in hybrid architectures.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	java, memory management, hardware acceleration
1	Jonathan Rohrer, Kubilay Atasu, Jan van Lunteren, Christoph Hagleitner	Memory-efficient distribution of regular expressions for fast deep packet inspection.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	regular expression, hardware acceleration, network intrusion detection, DFA, deep packet inspection
1	René Müller, Jens Teubner	FPGA: what's in it for a database?	SIGMOD Conference	2009	DBLP DOI BibTeX RDF	data processing vlsi, fpga, hardware acceleration
1	Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt	Efficient memory management for hardware accelerated Java Virtual Machines.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Java Virtual Machine, hardware acceleration, Dynamic memory management
1	Ning-Yi Xu, Xiongfei Cai, Rui Gao, Lei Zhang, Feng-Hsiung Hsu	FPGA Acceleration of RankBoost in Web Search Engines.	TRETS	2009	DBLP DOI BibTeX RDF	FPGA, hardware acceleration
1	Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar, Hans Peter Graf	A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines.	FCCM	2009	DBLP DOI BibTeX RDF	Machine Learning, FPGAs, Support Vector Machines, Parallel Architectures, Hardware Acceleration
1	Xavier Llorà, Anusha Priya, Rohit Bhargava	Observer-invariant histopathology using genetics-based machine learning.	Natural Computing	2009	DBLP DOI BibTeX RDF	Observer-invariant histopathology, Vector instruction, MPI, Learning Classifier Systems, Hardware acceleration, Massive parallelism, Genetics-based machine learning, SSE2
1	Yotam Livny, Zvi Kogan, Jihad El-Sana	Seamless patches for GPU-based terrain rendering.	The Visual Computer	2009	DBLP DOI BibTeX RDF	Level-of-detail rendering, Hardware acceleration, Terrain visualization, View-dependent rendering
1	Patrik Bichsel, Jan Camenisch, Thomas Groß, Victor Shoup	Anonymous credentials on a standard java card.	ACM Conference on Computer and Communications Security	2009	DBLP DOI BibTeX RDF	privacy-enhancing systems, smart card, java card, anonymous credential systems
1	Weihang Zhu	A study of parallel evolution strategy: pattern search on a GPU computing platform.	GEC Summit	2009	DBLP DOI BibTeX RDF	evolutionary computations, GPU, evolution strategy, pattern search
1	E. Riegel, T. Indinger, N. A. Adams	Numerical simulation of fluid flow on complex geometries using the Lattice-Boltzmann method and CUDA-enabled GPUs.	SIGGRAPH Posters	2009	DBLP DOI BibTeX RDF
1	João Paulo S. M. Lima, Veronica Teichrieb, Judith Kelner, Robert W. Lindeman	Standalone edge-based markerless tracking of fully 3-dimensional objects for handheld augmented reality.	VRST	2009	DBLP DOI BibTeX RDF	markerless tracking, computer vision, mobile, augmented reality, handheld
1	Vijay Nagarajan, Rajiv Gupta	Runtime monitoring on multicores via OASES.	Operating Systems Review	2009	DBLP DOI BibTeX RDF
1	Jiri Halak, Sven Ubik	MTPP - Modular Traffic Processing Platform.	DDECS	2009	DBLP DOI BibTeX RDF
1	Yuqiang Lu, Weiming Wang, Shifu Chen, Yongming Xie, Jing Qin, Wai-Man Pang, Pheng-Ann Heng	Accelerating Algebraic Reconstruction Using CUDA-Enabled GPU.	CGIV	2009	DBLP DOI BibTeX RDF
1	Lin Shi, Hao Chen, Jianhua Sun	vCUDA: GPU accelerated high performance computing in virtual machines.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Yahya Jan, Lech Józwiak	Survey of Advanced CABAC Accelerator Architectures for Future Multimedia.	ARC	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
1	Daniel Knoblauch, Falko Kuester	Focused Volumetric Visual Hull with Color Extraction.	ISVC	2009	DBLP DOI BibTeX RDF
1	Yahya Jan, Lech Józwiak	CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
1	Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail	FPGA Implementation of Elliptic Curve Point Multiplication over GF(2191).	ISA	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, polynomial inversion, field programmable gate arrays, Elliptic curve cryptography, Galois field, polynomial multiplication
1	E. Riegel, T. Indinger, N. A. Adams	Implementation of a Lattice-Boltzmann method for numerical fluid mechanics using the nVIDIA CUDA technology.	Computer Science - R&D	2009	DBLP DOI BibTeX RDF	Lattice-Boltzmann, LBUltra, GPU, CUDA, Fluid dynamics
1	Bin Sheng, Jian Zhu, Enhua Wu, Yanci Zhang	Lumiproxy: A Hybrid Representation of Image-Based Models.	J. Comput. Sci. Technol.	2009	DBLP DOI BibTeX RDF	lumiproxy, sampling, image-based rendering, surface fitting
1	Kenneth L. Rice, Tarek M. Taha, Christopher N. Vutsinas	Scaling analysis of a neocortex inspired cognitive model on the Cray XD1.	The Journal of Supercomputing	2009	DBLP DOI BibTeX RDF	Cognitive algorithms, Performance scaling, Parallel computing, Reconfigurable computing
1	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	FPGA multiprocessor, Multiprocessor, System-on-chip, Network-on-chip, MPEG-4, MPSoC, On-chip interconnection
1	Jason R. Villarreal, Walid A. Najjar	Compiled hardware acceleration of Molecular Dynamics code.	FPL	2008	DBLP DOI BibTeX RDF
1	Shimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael P. Ryan, Evangelos Vlachos	Flexible Hardware Acceleration for Instruction-Grain Program Monitoring.	ISCA	2008	DBLP DOI BibTeX RDF
1	Julien A. Vijverberg, Peter H. N. de With	Hardware acceleration for tracking by computing low-order geometric moments.	SiPS	2008	DBLP DOI BibTeX RDF
1	Tero Säntti, Joonas Tyystjärvi, Juha Plosila	A novel hardware acceleration scheme for java method calls.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Sebastian Fischmeister, Insup Lee, Robert Trausmuth	Hardware acceleration for verifiable, adaptive real-time communication.	ETFA	2008	DBLP DOI BibTeX RDF
1	Yotam Livny, Michael Press, Jihad El-Sana	Interactive GPU-based adaptive cartoon-style rendering.	The Visual Computer	2008	DBLP DOI BibTeX RDF	Cartoon rendering, Hardware acceleration, View-dependent rendering
1	Alexander Repenning, Andri Ioannidou	End-user visualizations.	AVI	2008	DBLP DOI BibTeX RDF	real-time image warping, end-user programming, 3D graphics
1	Alexander Repenning, Andri Ioannidou	Agent warp engine: formula based shape warping for networked applications.	AVI	2008	DBLP DOI BibTeX RDF	collective simulations, real-time image warping, end-user programming, spreadsheets, 3D graphics, end-user development
1	Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave	A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator.	ASAP	2008	DBLP DOI BibTeX RDF
1	Yang Yu, Xinyi Tang, Haijiao Cai, Yuanlin Chen, Sili Gao	3D Simulation of Real-Time Infrared Scene Based on DSP.	CSSE	2008	DBLP DOI BibTeX RDF
1	Hariharan G. Lalgudi, Michael W. Marcellin, Ali Bilgin, Mariappan S. Nadar	Lifting-Based View Compensated Compression of Volume Rendered Images for Efficient Remote Visualization.	DCC	2008	DBLP DOI BibTeX RDF	view compensation, volume rendering, JPEG2000
1	Allen C. Cheng	A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia Workloads.	DELTA	2008	DBLP DOI BibTeX RDF	Instruction Fusion, Mobile Embedded SoC, Portable Multimedia, Energy Efficiency