Search results for "Hardware implementations"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Svetla Nikova, Vincent Rijmen, Martin Schläffer	Using Normal Bases for Compact Hardware Implementations of the AES S-Box.	SCN	2008	DBLP DOI BibTeX RDF	AES, hardware implementation, S-box, normal basis
2	Jens-Peter Kaps	Chai-Tea, Cryptographic Hardware Implementations of xTEA.	INDOCRYPT	2008	DBLP DOI BibTeX RDF	symmetric key algorithms, TEA, XTEA, FPGA, ASIC, Efficient implementation
2	Roman C. Kordasiewicz, Shahram Shirani	On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, quantization, hardware implementations, MPEG4
2	Roman C. Kordasiewicz, Shahram Shirani	On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, Quantization, hardware implementations, MPEG4
2	Martin Feldhofer, Johannes Wolkerstorfer	Strong Crypto for RFID Tags - A Comparison of Low-Power Hardware Implementations.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Nadia Nedjah, Luiza de Macedo Mourelle	Four Hardware Implementations for the M-ary Modular Exponentiation.	ITNG	2006	DBLP DOI BibTeX RDF
2	Stefan Mangard, Kai Schramm	Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations.	CHES	2006	DBLP DOI BibTeX RDF	Zero-Offset DPA, Zero-Input DPA, Delay Chains, AES, DPA, Masking, Glitches
2	Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald	Successfully Attacking Masked AES Hardware Implementations.	CHES	2005	DBLP DOI BibTeX RDF
2	Ali E. Abdallah, John Hawkins	Formal Behavioural Synthesis of Handel-C Parallel Hardware Implementations from Functional Specifications. (PDF / PS)	HICSS	2003	DBLP DOI BibTeX RDF
2	Nicolas Sklavos, Alexander A. Moldovyan, Odysseas G. Koufopavlou	Encryption and Data Dependent Permutations: Implementation Cost and Performance Evaluation.	MMM-ACNS	2003	DBLP DOI BibTeX RDF	DDP Transformations, CIKS-1, Block Cipher, Hardware Implementations, SPECTR-H64
2	Tim Grembowski, Roar Lien, Kris Gaj, Nghi Nguyen, Peter Bellows, Jaroslav Flidr, Tom Lehman, Brian Schott	Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512.	ISC	2002	DBLP DOI BibTeX RDF
1	Debrup Chakraborty, Cuauhtemoc Mancillas-López, Francisco Rodríguez-Henríquez, Palash Sarkar	Efficient Hardware Implementations of BRW Polynomials and Tweakable Enciphering Schemes.	IACR Cryptology ePrint Archive	2011	DBLP BibTeX RDF
1	Rodrigo Martins da Silva, Nadia Nedjah, Luiza de Macedo Mourelle	Hardware Implementations of MLP Artificial Neural Networks with Configurable Topology.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Nadia Nedjah, Rodrigo Martins da Silva, Luiza de Macedo Mourelle	Analog Hardware Implementations of Artificial Neural Networks.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Omar Ahmed, Shawki Areibi, Karanvir Chattha, Ben Kelly	PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability.	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Seamus Cawley, Fearghal Morgan	Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations.	ICANN	2011	DBLP DOI BibTeX RDF
1	Toru Akishita, Harunaga Hiwatari	Very Compact Hardware Implementations of the Blockcipher CLEFIA.	Selected Areas in Cryptography	2011	DBLP DOI BibTeX RDF
1	Erich Wenger, Michael Hutter	Exploring the Design Space of Prime Field vs. Binary Field ECC-Hardware Implementations.	NordSec	2011	DBLP DOI BibTeX RDF
1	Cuauhtemoc Mancillas-López, Debrup Chakraborty, Francisco Rodríguez-Henríquez	Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF
1	Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes	Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL.	UKSim	2010	DBLP DOI BibTeX RDF
1	Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki	Hardware Implementations of Hash Function Luffa.	HOST	2010	DBLP DOI BibTeX RDF
1	Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep Pande, Fearghal Morgan	An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations.	ICES	2010	DBLP DOI BibTeX RDF
1	Abdulkadir Akin, Aydin Aysu, Onur Can Ulusel, Erkay Savas	Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing.	SIN	2010	DBLP DOI BibTeX RDF
1	Allen Leung, Nicolas Vasilache, Benoît Meister, Muthu Manikandan Baskaran, David Wohlford, Cédric Bastoul, Richard Lethin	A mapping path for multi-GPGPU accelerated computers from a portable high level programming abstraction.	GPGPU	2010	DBLP DOI BibTeX RDF	compiler optimziation, parallelization, GPGPU, CUDA, polyhedral model, automatic translation
1	Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar	Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.	DAC	2010	DBLP DOI BibTeX RDF	scalable effort, support vector machines, low power design, recognition, mining, approximate computing
1	Young-Jin Yoon, Nicola Concer, Michele Petracca, Luca P. Carloni	Virtual channels vs. multiple physical networks: a comparative analysis.	DAC	2010	DBLP DOI BibTeX RDF	channel slicing, network-on-chip, virtual channel
1	Benjamin Vigoda, David Reynolds, Jeffrey Bernstein, Theophane Weber, Bill Bradley	Low power logic for statistical inference.	ISLPED	2010	DBLP DOI BibTeX RDF	device physics, probability programming language, stochastic circuits, fault tolerance, markov chain monte carlo, generative model, belief propagation, gibbs sampling, probabilistic graphical model
1	Stefan Tillich, Martin Feldhofer, Wolfgang Issovits, Thomas Kern, Hermann Kureck, Michael Mühlberghuber, Georg Neubauer, Andreas Reiter, Armin Köfler, Mathias Mayrhofer	Compact Hardware Implementations of the SHA-3 Candidates ARIRANG, BLAKE, Gröstl, and Skein.	IACR Cryptology ePrint Archive	2009	DBLP BibTeX RDF
1	Giacomo de Meulenaer, Christophe Petit, Jean-Jacques Quisquater	Hardware Implementations of a Variant of the Zémor-Tillich Hash Function: Can a Provably Secure Hash Function be very efficient ?	IACR Cryptology ePrint Archive	2009	DBLP BibTeX RDF
1	Stefan Tillich, Martin Feldhofer, Mario Kirschbaum, Thomas Plos, Jörn-Marc Schmidt, Alexander Szekely	High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash, ECHO, Fugue, Gröstl, Hamsi, JH, Keccak, Luffa, Shabal, SHAvite-3, SIMD, and Skein.	IACR Cryptology ePrint Archive	2009	DBLP BibTeX RDF
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Fine-grain performance scaling of soft vector processors.	CASES	2009	DBLP DOI BibTeX RDF	VESPA, soft vector processor, viram, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
1	Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam	A DP-network for optimal dynamic routing in network-on-chip.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	optimal and sub-optimal routing, dynamic programming, network-on-chip, adaptive routing
1	Timothy F. Beatty, Eric E. Aubanel, Kenneth B. Kent	Customizable bit-width in an OpenMP-based circuit design tool.	FPGA	2009	DBLP DOI BibTeX RDF	handelc, hardware specification, openmp
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
1	Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja	A reconfigurable stochastic architecture for highly reliable computing.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	stochastic logic, reconfigurable architecture, reliable computing
1	Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero	EazyHTM: eager-lazy hardware transactional memory.	MICRO	2009	DBLP DOI BibTeX RDF	EazyHTM, transactional memory
1	Albert G. Greenberg, James R. Hamilton, Navendu Jain, Srikanth Kandula, Changhoon Kim, Parantap Lahiri, David A. Maltz, Parveen Patel, Sudipta Sengupta	VL2: a scalable and flexible data center network.	SIGCOMM	2009	DBLP DOI BibTeX RDF	commoditization, data center network
1	Feng Chen, David A. Koufaty, Xiaodong Zhang	Understanding intrinsic characteristics and system implications of flash memory based solid state drives.	SIGMETRICS/Performance	2009	DBLP DOI BibTeX RDF	hard disk drive, flash memory, solid state drive
1	Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith	SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	System design, hardware/software codesign
1	Robert P. McEvoy, Colin C. Murphy, William P. Marnane, Michael Tunstall	Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs.	TRETS	2009	DBLP DOI BibTeX RDF	secure logic, FPGA, Side-channel attacks, DPA, Whirlpool
1	Weirong Jiang, Viktor K. Prasanna	A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification.	ASAP	2009	DBLP DOI BibTeX RDF
1	Julien Lamoureux, Tony Field, Wayne Luk	Accelerating a Virtual Ecology Model with FPGAs.	ASAP	2009	DBLP DOI BibTeX RDF
1	Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke	Bridging the computation gap between programmable processors and hardwired accelerators.	HPCA	2009	DBLP DOI BibTeX RDF
1	Philip Werner Frey, Gustavo Alonso	Minimizing the Hidden Cost of RDMA.	ICDCS	2009	DBLP DOI BibTeX RDF
1	Benjamin J. Cohen, Jeffrey Byrne	Inertial aided SIFT for time to collision estimation.	ICRA	2009	DBLP DOI BibTeX RDF
1	Herianto, Daisuke Kurabayashi	Realization of an artificial pheromone system in random data carriers using RFID tags for autonomous navigation.	ICRA	2009	DBLP DOI BibTeX RDF
1	Weidong Zhang, Baocang Wang, Yupu Hu	A New Knapsack Public-Key Cryptosystem.	IAS	2009	DBLP DOI BibTeX RDF
1	Hugo Hedberg, Petr Dokládal, Viktor Öwall	Binary Morphology With Spatially Variant Structuring Elements: Algorithm and Architecture.	IEEE Transactions on Image Processing	2009	DBLP DOI BibTeX RDF
1	Junfeng Fan, Frederik Vercauteren, Ingrid Verbauwhede	Faster -Arithmetic for Cryptographic Pairings on Barreto-Naehrig Curves.	CHES	2009	DBLP DOI BibTeX RDF	BN curves, Pairings, Modular reduction
1	William L. Harrison, Adam M. Procter, Jason Agron, Garrin Kimmell, Gerard Allwein	Model-Driven Engineering from Modular Monadic Semantics: Implementation Techniques Targeting Hardware and Software.	DSL	2009	DBLP DOI BibTeX RDF
1	Minkyu Kim, Jung Hee Cheon, Jin Hong	Subset-Restricted Random Walks for Pollard rho Method on Fpm.	Public Key Cryptography	2009	DBLP DOI BibTeX RDF	Pollard rho method, pairing, normal basis, discrete logarithm problem
1	Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail	FPGA Implementation of Elliptic Curve Point Multiplication over GF(2191).	ISA	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, polynomial inversion, field programmable gate arrays, Elliptic curve cryptography, Galois field, polynomial multiplication
1	Kenneth L. Rice, Tarek M. Taha, Christopher N. Vutsinas	Scaling analysis of a neocortex inspired cognitive model on the Cray XD1.	The Journal of Supercomputing	2009	DBLP DOI BibTeX RDF	Cognitive algorithms, Performance scaling, Parallel computing, Reconfigurable computing
1	Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander	Automated Design Space Exploration for DSP Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	VLSI, Synthesis, Throughput, DSP, RTL, FIR filter, Hardware design, Power dissipation, Area
1	Yu Han, Xuecheng Zou, Zhenglin Liu, Yi-cheng Chen	Efficient DPA Attacks on AES Hardware Implementations.	IJCNS	2008	DBLP DOI BibTeX RDF
1	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh	Chosen-message SPA attacks against FPGA-based RSA hardware implementations.	FPL	2008	DBLP DOI BibTeX RDF
1	Jesse Scott, Michael Pusateri, Muhammad Umar Mushtaq	Comparison of 2D median filter hardware implementations for real-time stereo video.	AIPR	2008	DBLP DOI BibTeX RDF
1	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh	Enhanced power analysis attack using chosen message against RSA hardware implementations.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Akashi Satoh	ASIC hardware implementations for 512-bit hash function Whirlpool.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Shinsaku Kiyomoto, Toshiaki Tanaka, Kouichi Sakurai	FPGA-Targeted Hardware Implementations of K2.	SECRYPT	2008	DBLP BibTeX RDF
1	Sami Khanfir, Mohamed Jemni	Reconfigurable Hardware Implementations for Lifting-Based DWT Image Processing Algorithms.	ICESS	2008	DBLP DOI BibTeX RDF
1	Luk Van Ertvelde, Lieven Eeckhout	Dispersing proprietary applications as benchmarks through code mutation.	ASPLOS	2008	DBLP DOI BibTeX RDF	benchmark generation, code mutation
1	Amir Hormati, Manjunath Kudlur, Scott A. Mahlke, David F. Bacon, Rodric M. Rabbah	Optimus: efficient realization of streaming applications on FPGAs.	CASES	2008	DBLP DOI BibTeX RDF	optimization, FPGA, embedded systems, compiler, streaming, heterogeneous
1	Arash Ahmadi, Mark Zwolinski	Symbolic noise analysis approach to computational hardware optimization.	DAC	2008	DBLP DOI BibTeX RDF	word-length optimization, high level synthesis, computer arithmetic, computational error
1	Juan Hamers, Lieven Eeckhout	Automated hardware-independent scenario identification.	DAC	2008	DBLP DOI BibTeX RDF	scenario-based design, DVFS, video-decoding
1	Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel	Formal datapath representation and manipulation for implementing DSP transforms.	DAC	2008	DBLP DOI BibTeX RDF	high-level synthesis, streaming, discrete Fourier transform, linear transform
1	Ishaan L. Dalal, Deian Stefan	A hardware framework for the fast generation of multiple long-period random number streams.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, parallelized architecture, random number generator, mersenne twister
1	Mei-Hsuan Lu, Peter Steenkiste, Tsuhan Chen	Using commodity hardware platform to develop and evaluate CSMA protocols.	WINTECH	2008	DBLP DOI BibTeX RDF	host-based testbed, timing precision, CSMA
1	Kimmo Roimela, Tomi Aarnio, Joonas Itäranta	Efficient high dynamic range texture compression.	SI3D	2008	DBLP DOI BibTeX RDF	compression, texture, image, graphics hardware, high dynamic range, HDR
1	Nicolas Alt, Christopher Claus, Walter Stechele	Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments.	DATE	2008	DBLP DOI BibTeX RDF
1	David Boland, George A. Constantinides	An FPGA-based implementation of the MINRES algorithm.	FPL	2008	DBLP DOI BibTeX RDF
1	Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler	Numerical function generators using bilinear interpolation.	FPL	2008	DBLP DOI BibTeX RDF
1	Spyridon Ninos, Apostolos Dollas	Modeling recursion data structures for FPGA-based implementation.	FPL	2008	DBLP DOI BibTeX RDF
1	Vlad Mihai Sima, Elena Moscu Panainte, Koen Bertels	Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform.	FPL	2008	DBLP DOI BibTeX RDF
1	T. I. Manish	A Location Based Security Implementation in Smart Home.	HPCC	2008	DBLP DOI BibTeX RDF
1	Tarik Arici, Elif Albuz, Yucel Altunbasak	Using non-spatial prior information in block-matching based motion estimation.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Nadia Nedjah, Luiza de Macedo Mourelle	Efficient Hardware for Modular Exponentiation using the Sliding-Window Method with Variable-Length Partitioning.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Tse-Wei Chen, Chih-Hao Sun, Jun-Ying Bai, Han-Ru Chen, Shao-Yi Chien	Architectural analyses of K-Means silicon intellectual property for image segmentation.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Zbigniew Kokosinski, Pawel Halesiak	FPGA Generators of Combinatorial Configurations in a Linear Array Model.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Yang Sun, Joseph R. Cavallaro	Unified decoder architecture for LDPC/turbo codes.	SiPS	2008	DBLP DOI BibTeX RDF
1	Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti	High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips.	IEEE Trans. Dependable Sec. Comput.	2008	DBLP DOI BibTeX RDF
1	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Cost-Efficient SHA Hardware Accelerators.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Marcin Gomulkiewicz, Miroslaw Kutylowski, Pawel Wlaz	Random Fault Attack against Shrinking Generator.	ALGOSENSORS	2008	DBLP DOI BibTeX RDF
1	Alexander Klimm, Oliver Sander, Jürgen Becker, Sylvain Subileau	A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA.	ARCS	2008	DBLP DOI BibTeX RDF	Hyperelliptic Curve Cryptography (HECC), FPGA, embedded systems, Public Key Cryptography (PKC), reconfigurable hardware
1	Matthias Raspe, Guido Lorenz, Stefan Müller 0002	Evaluating the Performance of Processing Medical Volume Data on Graphics Hardware.	Bildverarbeitung für die Medizin	2008	DBLP DOI BibTeX RDF
1	Tim Güneysu, Christof Paar	Ultra High Performance ECC over NIST Primes on Commercial FPGAs.	CHES	2008	DBLP DOI BibTeX RDF	FPGA, High-Performance, Elliptic Curve Cryptosystems
1	Michael Backes, Boris Köpf	Formally Bounding the Side-Channel Leakage in Unknown-Message Attacks.	ESORICS	2008	DBLP DOI BibTeX RDF
1	Nadia Nedjah, Rodrigo Martins da Silva, Luiza de Macedo Mourelle, Marcus Vinicius Carvalho da Silva	Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks.	ICANN	2008	DBLP DOI BibTeX RDF
1	Svetla Nikova, Vincent Rijmen, Martin Schläffer	Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches.	ICISC	2008	DBLP DOI BibTeX RDF	non-linear functions, Noekeon, DPA, sharing, S-box, masking, glitches
1	Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto	An Efficient Countermeasure against Side Channel Attacks for Pairing Computation.	ISPEC	2008	DBLP DOI BibTeX RDF	random value addition, side channel attacks, Tate pairing, ? T pairing
1	Bogdan Belean, Monica Borda, Albert Fazakas	Adaptive Microarray Image Acquisition System and Microarray Image Processing Using FPGA Technology.	KES	2008	DBLP DOI BibTeX RDF	FPGA Technology, Image Processing, Parallel Processing, cDNA Microarray
1	Theo D'Hondt	Are Bytecodes an Atavism?	S3	2008	DBLP DOI BibTeX RDF	Virtual machines, interpreters, bytecodes
1	Xu Guo, Zhimin Chen, Patrick Schaumont	Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Awais M. Kamboh, Andrew J. Mason, Karim G. Oweiss	Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	neural interface, data compression, discrete wavelet transform, B-spline, lifting
1	Christophe De Cannière, Bart Preneel	Trivium.	The eSTREAM Finalists	2008	DBLP DOI BibTeX RDF
1	Cuauhtemoc Mancillas-López, Debrup Chakraborty, Francisco Rodríguez-Henríquez	Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes.	IACR Cryptology ePrint Archive	2007	DBLP BibTeX RDF
1	Guerric Meurice de Dormale, Jean-Jacques Quisquater	High-speed hardware implementations of Elliptic Curve Cryptography: A survey.	Journal of Systems Architecture	2007	DBLP DOI BibTeX RDF
1	Alejandro Chinea Manrique De Lara, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany	Improving the Performance of PieceWise Linear Separation Incremental Algorithms for Practical Hardware Implementations	CoRR	2007	DBLP BibTeX RDF
1	Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede	Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations.	WISA	2007	DBLP DOI BibTeX RDF	SHA-256 (384,512), Iteration Bound Analysis, Throughput Optimum Architecture
1	Mehran Mozaffari Kermani, Arash Reyhani-Masoleh	A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard.	FDTC	2007	DBLP DOI BibTeX RDF