Search results for "Haridimos T. Vergos"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Haridimos T. Vergos, Giorgos Dimitrakopoulos	On Modulo 2^n+1 Adder Design.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Dimitris Bakalis, Haridimos T. Vergos, A. Spyrou	Efficient modulo 2n±1 squarers.	Integration	2011	DBLP DOI BibTeX RDF
1	Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos	Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion.	DSD	2011	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Dimitris Bakalis	On Implementing Efficient Modulo 2n + 1 Arithmetic Components.	Journal of Circuits, Systems, and Computers	2010	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou	Fast modulo 2n+1 multi-operand adders and residue generators.	Integration	2010	DBLP DOI BibTeX RDF
1	Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos	SUT-RNS Forward and Reverse Converters.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos	A Family of Area-Time Efficient Modulo 2n+1 Adders.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Dimitris Bakalis, Haridimos T. Vergos	Area-Efficient Multi-moduli Squarers for RNS.	DSD	2010	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Costas Efstathiou	Efficient modulo 2n+1 adder architectures.	Integration	2009	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Costas Efstathiou	A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Dimitris Bakalis	On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components.	DSD	2008	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Costas Efstathiou	Design of efficient modulo 2n+1 multipliers.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	D. Adamidis, Haridimos T. Vergos	RNS multiplication/sum-of-squares units.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos	An Efficient BIST Scheme for Non-Restoring Array Dividers.	DSD	2007	DBLP DOI BibTeX RDF
1	Dimitris Bakalis, K. Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos	A core generator for arithmetic cores and testing structures with a network interface.	Journal of Systems Architecture	2006	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Costas Efstathiou	Novel Modulo 2n + 1 Multipliers.	DSD	2006	DBLP DOI BibTeX RDF
1	Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos	Efficient Diminished-1 Modulo 2^n+1 Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Modulo 2^n+1 multipliers, Fermat number transform, computer arithmetic, VLSI design, residue number system
1	Haridimos T. Vergos, Costas Efstathiou	On the Design of Efficient Modular Adders.	Journal of Circuits, Systems, and Computers	2005	DBLP DOI BibTeX RDF
1	Nikolaos Kostaras, Haridimos T. Vergos	KoVer: A Sophisticated Residue Arithmetic Core Generator.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modified Booth Modulo 2n-1 Multipliers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Mersenne arithmetic, one's complement arithmetic, Booth multipliers, VLSI design, Residue Number System
1	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Fast Parallel-Prefix Modulo 2^n+1 Adders.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Costas Efstathiou	Diminished-1 Modulo 2n + 1 Squarer Design.	DSD	2004	DBLP DOI BibTeX RDF
1	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modulo 2n±1 Adder Design Using Select-Prefix Blocks.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures
1	Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou	Deterministic BIST for RNS Adders.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
1	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A Family of Parallel-Pre.x Modulo 2n - 1 Adders.	ASAP	2003	DBLP DOI BibTeX RDF
1	D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou	Efficient BIST schemes for RNS datapaths.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders.	ISCAS	2003	DBLP DOI BibTeX RDF
1	D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou	An Efficient BIST scheme for High-Speed Adders.	IOLTS	2003	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos	Diminished-One Modulo 2n+1 Adder Design.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders
1	Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou	On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation.	Journal of Systems Architecture	2002	DBLP DOI BibTeX RDF
1	Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos	On Accumulator-Based Bit-Serial Test Response Compaction Schemes.	ISQED	2001	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
1	Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos	High-Speed Parallel-Prefix Modulo 2n-1 Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders
1	Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos	Low Power BIST for Wallace Tree-Based Fast Multipliers.	ISQED	2000	DBLP DOI BibTeX RDF	Testing, Low Power, BIST, Multipliers, Wallace Trees
1	Dimitris Nikolos, Haridimos T. Vergos	On the Yield of VLSI Processors with On-Chip CPU Cache.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	on-chip CPU caches, partially good chips, Fault tolerance, yield enhancement
1	G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos	Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis	On Path Delay Fault Testing of Multiplexer - Based Shifters.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	C. Ninos, Haridimos T. Vergos, Dimitris Nikolos	Design and Analysis of On-Chip CPU Pipelined Caches.	VLSI	1999	DBLP BibTeX RDF
1	Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos	Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks.	EDCC	1999	DBLP DOI BibTeX RDF
1	Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas	Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks.	DATE	1999	DBLP DOI BibTeX RDF
1	Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing
1	Dimitris Nikolos, Haridimos T. Vergos	On the Yield of VLSI Processors with on-chip CPU Cache.	EDCC	1996	DBLP DOI BibTeX RDF	Indexing terms On-chip CPU caches, Partially good chips, Fault Tolerance, Yield Enhancement

Publications of "Haridimos T. Vergos" ( http://dblp.L3S.de/Authors/Haridimos_T._Vergos )