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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3 occurrences of 2 keywords
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Results
Found 10 publication records. Showing 10 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose |
An Energy-Efficient Memristive Threshold Logic Circuit.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose |
Design Considerations for Multilevel CMOS/Nano Memristive Memory.  |
JETC  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino |
Leveraging Memristive Systems in the Construction of Digital Logic Circuits.  |
Proceedings of the IEEE  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose |
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.  |
IEEE Trans. on Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose |
An Approach to Tolerate Process Related Variations in Memristor-Based Applications.  |
VLSI Design  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Garrett S. Rose |
A read-monitored write circuit for 1T1M multi-level memristor memories.  |
ISCAS  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang 0003 |
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory.  |
ACM Great Lakes Symposium on VLSI  |
2010 |
DBLP DOI BibTeX RDF |
CMOS/nano, memristor, multi level memories |
| 1 | Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon |
Inversion schemes for sublithographic programmable logic arrays.  |
IET Computers & Digital Techniques  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Harika Manem, Garrett S. Rose |
The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.  |
ACM Great Lakes Symposium on VLSI  |
2009 |
DBLP DOI BibTeX RDF |
cmos-nano, fpga |
| 1 | Harika Manem, Peter C. Paliwoda, Garrett S. Rose |
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.  |
ACM Great Lakes Symposium on VLSI  |
2008 |
DBLP DOI BibTeX RDF |
PMLA, FPGA, hybrid |
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