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Publications of "Harika Manem" ( http://dblp.L3S.de/Authors/Harika_Manem )

  Author page on DBLP  Author page in RDF  Community of Harika Manem in ASPL-2

Publication years (Num. hits)
2008 (1) 2009 (2) 2010 (1) 2011 (2) 2012 (4)
Publication types (Num. hits)
article(5) inproceedings(5)
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Found 10 publication records. Showing 10 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose An Energy-Efficient Memristive Threshold Logic Circuit. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose Design Considerations for Multilevel CMOS/Nano Memristive Memory. Search on Bibsonomy JETC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino Leveraging Memristive Systems in the Construction of Digital Logic Circuits. Search on Bibsonomy Proceedings of the IEEE The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose An Approach to Tolerate Process Related Variations in Memristor-Based Applications. Search on Bibsonomy VLSI Design The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Harika Manem, Garrett S. Rose A read-monitored write circuit for 1T1M multi-level memristor memories. Search on Bibsonomy ISCAS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang 0003 Design considerations for variation tolerant multilevel CMOS/Nano memristor memory. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF CMOS/nano, memristor, multi level memories
1Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon Inversion schemes for sublithographic programmable logic arrays. Search on Bibsonomy IET Computers & Digital Techniques The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Harika Manem, Garrett S. Rose The effects of logic partitioning in a majority logic based CMOS-NANO FPGA. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF cmos-nano, fpga
1Harika Manem, Peter C. Paliwoda, Garrett S. Rose A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF PMLA, FPGA, hybrid
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