Search results for "Hideharu Amano"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hideharu Amano	Foreword.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano	Vertical Link On/Off Control Methods for Wireless 3-D NoCs.	ARCS	2012	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration.	ARC	2012	DBLP DOI BibTeX RDF
1	Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano	Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano	A Leakage Efficient Data TLB Design for Embedded Processors.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano	A Leakage Efficient Instruction TLB Design for Embedded Processors.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs.	SIGARCH Computer Architecture News	2011	DBLP DOI BibTeX RDF
1	Amila Akagic, Hideharu Amano	High speed CRC with 64-bit generator polynomial on an FPGA.	SIGARCH Computer Architecture News	2011	DBLP DOI BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano	A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	routing, interconnection networks, Ethernet, PC clusters, deadlock avoidance
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga	Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano	An analytical network performance model for SIMD processor CSX600 interconnects.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura	On-chip detection methodology for break-even time of power gated function units.	ISLPED	2011	DBLP BibTeX RDF
1	Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano	A vertical bubble flow network using inductive-coupling for 3-D CMPs.	NOCS	2011	DBLP BibTeX RDF
1	Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano	The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator.	FPT	2011	DBLP DOI BibTeX RDF
1	Masayuki Kimura, Kazuei Hironaka, Hideharu Amano	Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations.	FPT	2011	DBLP DOI BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Array: A highly energy efficient reconfigurable accelerator.	FPT	2011	DBLP DOI BibTeX RDF
1	Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo	Geyser-2: The second prototype CPU with fine-grained run-time power gating.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano	A Dynamic Link-Width Optimization for Network-on-Chip.	RTCSA	2011	DBLP DOI BibTeX RDF
1	Tetsuya Nakahama, Masahiro Yamada, Masato Yoshimi, Hideharu Amano	Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster.	ICNC	2011	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano	Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.	ICNC	2011	DBLP DOI BibTeX RDF
1	Akihiro Shitara, Tetsuya Nakahama, Masahiro Yamada, Toshiaki Kamata, Yuri Nishikawa, Masato Yoshimi, Hideharu Amano	Vegeta: An Implementation and Evaluation of Development-Support Middleware on Multiple OpenCL Platform.	ICNC	2011	DBLP DOI BibTeX RDF
1	Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami	Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction.	ARC	2011	DBLP DOI BibTeX RDF
1	Kazuei Hironaka, Hideharu Amano	Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system.	SIGARCH Computer Architecture News	2010	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	Adaptive power gating for function units in a microprocessor.	ISQED	2010	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.	NOCS	2010	DBLP DOI BibTeX RDF	low power, Network-on-Chip, router, power gating
1	Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano	Wire congestion aware synthesis for a dynamically reconfigurable processor.	FPT	2010	DBLP DOI BibTeX RDF
1	Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano	Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.	FPT	2010	DBLP DOI BibTeX RDF
1	Yui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri	A datapath classification method for FPGA-based scientific application accelerator systems.	FPT	2010	DBLP DOI BibTeX RDF
1	Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo	Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano	MuCCRA-3: a low power dynamically reconfigurable processor array.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki	Reducing instruction TLB's leakage power consumption for embedded processors.	Green Computing Conference	2010	DBLP DOI BibTeX RDF
1	Phaophak Sirisuk, Fearghal Morgan, Tarek A. El-Ghazawi, Hideharu Amano (eds.)	Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. Proceedings	ARC	2010	DBLP DOI BibTeX RDF
1	Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer	A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster.	ARC	2010	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks.	NAS	2010	DBLP DOI BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching.	NAS	2010	DBLP DOI BibTeX RDF	non-minimal fully adaptive routing, NoC, deadlock-free routing, SAN, turn-model, virtual cut-through
1	Iver Stubdal, Arda Karaduman, Hideharu Amano	Code Compression with Split Echo Instructions.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano	Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IEEE Trans. Parallel Distrib. Syst.	2009	DBLP DOI BibTeX RDF
1	Hideharu Amano, Tadao Nakamura	Guest Editors' Introduction: ICFPT 2007.	TRETS	2009	DBLP DOI BibTeX RDF
1	Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano	Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator.	FPL	2009	DBLP DOI BibTeX RDF
1	Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano	MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.	FPL	2009	DBLP DOI BibTeX RDF
1	Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano	Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.	FPL	2009	DBLP DOI BibTeX RDF
1	Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano	Cache Controller Design on Ultra Low Leakage Embedded Processors.	ARCS	2009	DBLP DOI BibTeX RDF
1	Toru Sano, Yoshiki Saito, Hideharu Amano	Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.	ERSA	2009	DBLP BibTeX RDF
1	Hideharu Amano	Japanese Dynamically Reconfigurable Processors.	ERSA	2009	DBLP BibTeX RDF
1	Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano	A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.	ERSA	2009	DBLP BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano	Performance Analysis of ClearSpeed's CSX600 Interconnects.	ISPA	2009	DBLP DOI BibTeX RDF	ClearSpeed, CSX600, performance evaluation, SIMD, NoC
1	Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano	Evaluation of a multicore reconfigurable architecture with variable core sizes.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano	An on/off link activation method for low-power ethernet in PC clusters.	IPDPS	2009	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano	An On/Off Link Activation Method for Power Regulation in InfiniBand.	PDPTA	2009	DBLP BibTeX RDF
1	Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura	Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri	Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator.	ARC	2009	DBLP DOI BibTeX RDF
1	Hideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri	A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA.	ReConFig	2009	DBLP DOI BibTeX RDF	Biochemistry, Kinetic simulation, FPGA, Design automation
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga	Prediction router: Yet another low latency on-chip router architecture.	HPCA	2009	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	Balanced Dimension-Order Routing for k-ary n-cubes.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	Vu Manh Tuan, Hideharu Amano	A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Vu Manh Tuan, Hideharu Amano	A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Vasutan Tunbunheng, Hideharu Amano	A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano	Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.	FPL	2008	DBLP DOI BibTeX RDF
1	Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsusmi, Vasutan Tunbunheng, Hideharu Amano	Power reduction techniques for Dynamically Reconfigurable Processor Arrays.	FPL	2008	DBLP DOI BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi	A link removal methodology for Networks-on-Chip on reconfigurable systems.	FPL	2008	DBLP DOI BibTeX RDF
1	Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano	Practical implementation of a network-based stochastic biochemical simulation system on an FPGA.	FPL	2008	DBLP DOI BibTeX RDF
1	Vu Manh Tuan, Hideharu Amano	A Method for Capturing State Data on Dynamically Reconfigurable Processors.	ERSA	2008	DBLP BibTeX RDF
1	Masaru Kato, Yohei Hasegawa, Hideharu Amano	Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs.	ERSA	2008	DBLP BibTeX RDF
1	Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston	A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, Network-on-Chip, routing algorithm, deadlock avoidance, on-chip network
1	Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano	Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF	low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang	Run-time power gating of on-chip routers using look-ahead routing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Vu Manh Tuan, Hideharu Amano	A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.	ARC	2008	DBLP DOI BibTeX RDF
1	Yuken Kishimoto, Shinichiro Haruyama, Hideharu Amano	Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor.	ReConFig	2008	DBLP DOI BibTeX RDF	Software-Defined Radio, Reconfigurable Processor, Viterbi Decoder
1	Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano	Three-Dimensional Layout of On-Chip Tree-Based Networks.	ISPAN	2008	DBLP DOI BibTeX RDF	Fat H-Tree, Network-on-Chip, Fat Tree, 3-D IC
1	Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	A fine-grain dynamic sleep control scheme in MIPS R3000.	ICCD	2008	DBLP DOI BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano	Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano	Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Network Interface Controller, RHiNET, PC Clusters, System Area Network
1	Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano	An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	interconnection networks, Adaptive routing, PC clusters, deadlock avoidance, irregular topologies, system area networks, turn model
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.	FPL	2007	DBLP DOI BibTeX RDF
1	Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri	A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator.	FPL	2007	DBLP DOI BibTeX RDF
1	Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka	A High Speed License Plate Recognition System on an FPGA.	FPL	2007	DBLP DOI BibTeX RDF
1	Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano	FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method.	FPL	2007	DBLP DOI BibTeX RDF
1	Yohei Hasegawa, Hideharu Amano	Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays.	FPL	2007	DBLP DOI BibTeX RDF
1	Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano	Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor.	ERSA	2007	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano	Performance Improvement Methodology for ClearSpeed's CSX600.	ICPP	2007	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.	ICPP	2007	DBLP DOI BibTeX RDF
1	Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo	Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.	PDPTA	2007	DBLP BibTeX RDF
1	Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka	Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA.	CIT	2007	DBLP DOI BibTeX RDF
1	Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano	Performance evaluation on low-latency communication mechanism of DIMMnet-2.	Parallel and Distributed Computing and Networks	2007	DBLP BibTeX RDF
1	Hideharu Amano	A Survey on Dynamically Reconfigurable Processors.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano	A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.	IEEE Trans. Parallel Distrib. Syst.	2006	DBLP DOI BibTeX RDF	table-lookup routing, interconnection networks, Networks-on-chips, streaming processing, reconfigurable systems, on-chip interconnects
1	Yasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano	Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip.	FPL	2006	DBLP DOI BibTeX RDF
1	Hideharu Amano, Yohei Hasegawa, Shohei Abe, K. Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura	A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.	FPL	2006	DBLP DOI BibTeX RDF
1	Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano	An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems.	FPL	2006	DBLP DOI BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano	A Parametric Study of Scalable Interconnects on FPGAs.	ERSA	2006	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks.	ISCA PDCS	2006	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels.	ISPA	2006	DBLP DOI BibTeX RDF

Publications of "Hideharu Amano" ( http://dblp.L3S.de/Authors/Hideharu_Amano )