| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto |
Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design.  |
IEICE Transactions  |
2011 |
DBLP BibTeX RDF |
|
| 1 | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
F-Scan: A DFT Method for Functional Scan at RTL. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Chia Yee Ooi, Hideo Fujiwara |
A New Design-for-Testability Method Based on Thru-Testability. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara |
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara |
Faster-than-at-speed test for increased test quality and in-field reliability. |
ITC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara |
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
automatic test pattern generation, scan-based test, high-level testing |
| 1 | Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara |
Temperature-Variation-Aware Test Pattern Optimization. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto |
Secure scan design using shift register equivalents against differential behavior attack. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara |
Design and Optimization of Transparency-Based TAM for SoC Test. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara |
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara |
A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara |
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
|
| 1 | Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara |
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
Constrained ATPG for functional RTL circuits using F-Scan. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara |
Enabling False Path Identification from RTL for Reducing Design and Test Futileness. |
DELTA |
2010 |
DBLP DOI BibTeX RDF |
path mapping, false path, functional equivalence, high level testing |
| 1 | Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara |
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara |
Seed Ordering and Selection for High Quality Delay Test. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara |
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara |
Graph theoretic approach for scan cell reordering to minimize peak shift power. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
power droop, scan chain reordering, peak power |
| 1 | Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara |
Test pattern selection to optimize delay test quality with a limited size of test set. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara |
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hideo Fujiwara, Marie Engelene J. Obien |
Secure and testable scan design using extended de Bruijn graphs. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara |
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh |
On Minimization of Test Application Time for RAS. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Random Access Scan (RAS), DFT, Scan Design |
| 1 | Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto |
SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara |
A synthesis method to propagate false path information from RTL to gate level. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara |
Aging test strategy and adaptive test scheduling for SoC failure prediction. |
IOLTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara |
RTL DFT techniques to enhance defect coverage for functional test sequences. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara |
Partial Scan Approach for Secret Information Protection. |
European Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
Cryptographic circuits, Security, Testability, Balanced structure |
| 1 | Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara |
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
TAM design, thermal-aware test, wrapper design, test scheduling, SOC test |
| 1 | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
Fast false path identification based on functional unsensitizability using RTL information. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara |
Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. |
DISC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara |
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara |
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara |
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
Scheduling Power-Constrained Tests through the SoC Functional Bus. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara |
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara |
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara |
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi |
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara |
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara |
Localized random access scan: Towards low area and routing overhead. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Hideo Fujiwara |
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara |
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara |
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong Xiang, Mingjing Chen, Hideo Fujiwara |
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Random testability, scan enable signal, weighted random testing, scan-based BIST |
| 1 | Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara |
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Scan forest, test application cost, test data volume, test power |
| 1 | Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara |
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilia Polian, Hideo Fujiwara |
Functional Constraints vs. Test Compression in Scan-Based Delay Testing. |
J. Electronic Testing |
2007 |
DBLP DOI BibTeX RDF |
Overtesting prevention, Scan-based delay test, Test compression, Functional constraints |
| 1 | Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara |
Fast and effective fault simulation for path delay faults based on selected testable paths. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara |
A DFT Method for Time Expansion Model at Register Transfer Level. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara |
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. |
European Test Symposium |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Dan Zhao, Unni Chandran, Hideo Fujiwara |
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara |
TAM Design and Optimization for Transparency-Based SoC Test. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
TAM design, transparency, ILP, SoC test |
| 1 | Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara |
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
multi-clock domain, wrapper design, SoC, test scheduling, embedded core test |
| 1 | Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara |
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable union wrapper, system-on-a-chip, test scheduling, test access mechanism |
| 1 | Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara |
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara |
Efficient path delay test generation based on stuck-at test generation using checker circuitry. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara |
A Low Power Deterministic Test Using Scan Chain Disable Technique. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara |
Effect of BIST Pretest on IC Defect Level. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara |
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara |
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Hideo Fujiwara |
Design for consecutive transparency method of RTL circuits. |
Systems and Computers in Japan |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Erik Larsson, Hideo Fujiwara |
System-on-chip test scheduling with reconfigurable core wrappers. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell |
Electrical Behavior of GOS Fault affected Domino Logic Cell. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
Gate-Oxide Short (GOS), Electrical analysis Boolean test, Domino logic, Defect modeling |
| 1 | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara |
A memory grouping method for sharing memory BIST logic. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara |
BIST Pretest of ICs: Risks and Benefits. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilia Polian, Hideo Fujiwara |
Functional constraints vs. test compression in scan-based delay testing. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
overtesting prevention, scan-based delay test, test compression, functional constraints |
| 1 | Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara |
Power-constrained test scheduling for multi-clock domain SoCs. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
multi-clock domain SoC, power consumption, test scheduling, test access mechanism |
| 1 | Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara |
Low-Cost Hardening of Image Processing Applications Against Soft Errors. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia Yee Ooi, Hideo Fujiwara |
A New Class of Sequential Circuits with Acyclic Test Generation Complexity. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
Power-Constrained SOC Test Schedules through Utilization of Functional Buses. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun |
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara |
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara |
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara |
Classification of Sequential Circuits Based on tauk Notation and Its Applications. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Delay Fault Testing of Processor Cores in Functional Mode. |
IEICE Transactions |
2005 |
DBLP BibTeX RDF |
|
| 1 | Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara |
Improving test effectiveness of scan-based BIST by scan chain partitioning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara |
Design and analysis of multiple weight linear compactors of responses containing unknown values. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Testing Superscalar Processors in Functional Mode. |
FPL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara |
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip, power consumption, test scheduling, test access mechanism, consecutive testability |
| 1 | Dong Xiang, Kaiwei Li, Hideo Fujiwara |
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong Xiang, Ming-Jing Chen, Hideo Fujiwara |
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
Test signal, random testability, weighted random testing, scan-based BIST |
| 1 | Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara |
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
strong testability, partially strong testability, complete fault efficiency, design-for-testability, data paths |
| 1 | Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara |
An Effective Design for Hierarchical Test Generation Based on Strong Testability. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
Hierarchical test generation, strong testability, datapath, test plan |
| 1 | Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki |
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara |
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja |
A Class of Linear Space Compactors for Enhanced Diagnostic. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Instruction-based delay fault self-testing of pipelined processor cores. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara |
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. |
IEICE Transactions |
2004 |
DBLP BibTeX RDF |
|
| 1 | Erik Larsson, Hideo Fujiwara |
Preemptive System-on-Chip Test Scheduling. |
IEICE Transactions |
2004 |
DBLP BibTeX RDF |
|
| 1 | Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng |
Efficient test solutions for core-based designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara |
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
scan and non-scan, fault efficiency, ATPG |
| 1 | Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian |
Design & Test Education in Asia. |
IEEE Design & Test of Computers |
2004 |
DBLP BibTeX RDF |
|
| 1 | Chia Yee Ooi, Hideo Fujiwara |
Classification of Sequential Circuits Based on ?k Notation. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
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