Search results for "Hideo Ito"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kentaroh Katoh, Kazuteru Namba, Hideo Ito	An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Construction of BILBO FF with Soft-Error-Tolerant Capability.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Two-rail logic circuit, overtesting, testability, monotone function, path delay fault testing
1	Kazuteru Namba, Kengo Nakashima, Hideo Ito	Single-Event-Upset Tolerant RS Flip-Flop with Small Area.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Kazuteru Namba, Takashi Ikeda, Hideo Ito	Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Chiba Scan Delay Fault Testing with Short Test Application Time.	J. Electronic Testing	2010	DBLP DOI BibTeX RDF
1	Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito	Quantitative Evaluation of Integrity for Remote System Using the Internet.	PRDC	2010	DBLP DOI BibTeX RDF
1	Kentaroh Katoh, Kazuteru Namba, Hideo Ito	A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Kentaroh Katoh, Kazuteru Namba, Hideo Ito	Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Kentaroh Katoh, Kazuteru Namba, Hideo Ito	Design for Delay Fault Testability of 2-Rail Logic Circuits.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Shuangyu Ruan, Kazuteru Namba, Hideo Ito	Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Kazuteru Namba, Yoshikazu Matsui, Hideo Ito	Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	IP core testing, Fixing-flipping coding, Fixing-shifting-flipping coding, Test compression, Reconfigurable network
1	Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito	Dependability Evaluation for Internet-Based Remote Systems.	PRDC	2009	DBLP DOI BibTeX RDF
1	Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito	A Delay Measurement Technique Using Signature Registers.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Takumi Hoshi, Kazuteru Namba, Hideo Ito	Testing of Switch Blocks in Three-Dimensional FPGA.	DFT	2009	DBLP DOI BibTeX RDF
1	Masato Kitakami, Bochuan Cai, Hideo Ito	A Checkpointing Method with Small Checkpoint Latency.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Toshinori Takabatake, Tomoki Nakamigawa, Hideo Ito	Connectivity of Generalized Hierarchical Completely-Connected Networks.	Journal of Interconnection Networks	2008	DBLP DOI BibTeX RDF
1	Yoichi Sasaki, Kazuteru Namba, Hideo Ito	Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
1	Kazuteru Namba, Hideo Ito	Path Delay Fault Test Set for Two-Rail Logic Circuits.	PRDC	2008	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Delay Fault Testability on Two-Rail Logic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
1	Shuangyu Ruan, Kazuteru Namba, Hideo Ito	Soft Error Hardened FF Capable of Detecting Wide Error Pulse.	DFT	2008	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Low-Cost IP Core Test Using Tri-Template-Based Codes.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Takashi Ikeda, Kazuteru Namba, Hideo Ito	Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.	DFT	2007	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Kentaroh Katoh, Hideo Ito	Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.	DFT	2007	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Redundant Design for Wallace Multiplier.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Proposal of Testable Multi-Context FPGA Architecture.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kentaroh Katoh, Hideo Ito	Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.	European Test Symposium	2006	DBLP DOI BibTeX RDF	Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
1	Gang Zeng, Hideo Ito	Concurrent core test for SOC using shared test set and scan chain disable.	DATE	2006	DBLP DOI BibTeX RDF
1	Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito	Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.	DFT	2006	DBLP DOI BibTeX RDF
1	Yoichi Sasaki, Kazuteru Namba, Hideo Ito	Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.	DFT	2006	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Scan Design for Two-Pattern Test without Extra Latches.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Design of Defect Tolerant Wallace Multiplier.	PRDC	2005	DBLP DOI BibTeX RDF
1	Kentaroh Katoh, Abderrahim Doumar, Hideo Ito	Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree.	ICCD	2005	DBLP DOI BibTeX RDF
1	Manabu Sueishi, Masato Kitakami, Hideo Ito	Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking.	PRDC	2004	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core.	VTS	2004	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Non-Intrusive Test Compression for SOC Using Embedded FPGA Core.	DFT	2004	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Gang Zeng, Hideo Ito	Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core.	DFT	2003	DBLP DOI BibTeX RDF
1	Toshinori Takabatake, Masato Kitakami, Hideo Ito	Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks.	PRDC	2002	DBLP DOI BibTeX RDF
1	Lihong Tong, Kazuki Suzuki, Hideo Ito	Optimal Seed Generation for Delay Fault Detection BIST.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
1	Toshinori Takabatake, Masato Kitakami, Hideo Ito	A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks.	IASTED PDCS	2002	DBLP BibTeX RDF
1	Masato Kitakami, Shunji Kubota, Hideo Ito	Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction.	PRDC	2001	DBLP DOI BibTeX RDF	Referential transparency, Fault tolerance, functional programming, message logging, graph reduction
1	Toshinori Takabatake, Masato Kitakami, Hideo Ito	Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks.	PRDC	2001	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
1	Abderrahim Doumar, Hideo Ito	Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. (PDF / PS)	DFT	2000	DBLP DOI BibTeX RDF
1	Mikio Yagi, Keiichi Kaneko, Hideo Ito	LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments.	PRDC	1999	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	An Automatic Testing and Diagnosis for FPGAs.	PRDC	1999	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Hideo Ito	Testing the Logic Cells and Interconnect Resources for FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
1	Keiichi Kaneko, Hideo Ito	Fault-Tolerant Routing Algorithms for Hypercube Networks. (PDF / PS)	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
1	Abderrahim Doumar, Satoshi Kaneko, Hideo Ito	Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF
1	Toshinori Takabatake, Keiichi Kaneko, Hideo Ito	Generalized Hierarchical Completely-Connected Networks.	ISPAN	1999	DBLP DOI BibTeX RDF	completely-connected network, constant node degree, interconnection network, block, hierarchical network, generalized network
1	Hammadi Nait-Charif, Hideo Ito	Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons.	Journal of Intelligent and Robotic Systems	1998	DBLP DOI BibTeX RDF	noise injection, fault tolerance, generalization, feedforward neural networks
1	Hideo Ito, Takashi Yagi	Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks.	DFT	1994	DBLP BibTeX RDF
1	Hideo Ito	A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube.	DFT	1993	DBLP BibTeX RDF

Publications of "Hideo Ito" ( http://dblp.L3S.de/Authors/Hideo_Ito )