Search results for "Hidetoshi Onodera"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera	Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera	A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera	Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera	Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation.	ISQED	2011	DBLP DOI BibTeX RDF
1	Hidetoshi Onodera	Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera	A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera	An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera	A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Hiroki Sunagawa, Hidetoshi Onodera	Variation-tolerant design of D-flipflops.	SoCC	2010	DBLP DOI BibTeX RDF
1	SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera	A design procedure of predictive RF MOSFET model for compatibility with ITRS.	SoCC	2010	DBLP DOI BibTeX RDF
1	Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera	Statistical Gate Delay Model for Multiple Input Switching.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Erect of regularity-enhanced layout on printability and circuit performance of standard cells.	ISQED	2009	DBLP DOI BibTeX RDF
1	Gennady Gildenblat, Hidetoshi Onodera	Modeling of passive elements and reliability.	CICC	2009	DBLP DOI BibTeX RDF
1	Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe	Dependable VLSI: device, design and architecture: how should they cooperate?	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera	Timing Analysis Considering Temporal Supply Voltage Fluctuation.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera	Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera	A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
1	Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera	Statistical gate delay model for Multiple Input Switching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Hidetoshi Onodera	Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, routing, variation, yield enhancement
1	Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera	A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera	Timing Analysis Considering Spatial Power/Ground Level Variation.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Hirokazu Muta, Hidetoshi Onodera	Manufacturability-Aware Design of Standard Cells.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera	A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera	Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera	Worst-case delay analysis considering the variability of transistors and interconnects.	ISPD	2007	DBLP DOI BibTeX RDF	worst-case delay, interconnect, process variation
1	Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera	A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.	ASP-DAC	2007	DBLP DOI BibTeX RDF	on-chip signaling circuit, impedance-unmatched CML driver, differential transmission-line, CML receiver, CML buffer, load resistance tuning, 10 Gbit/s, CMOS technology, power reduction, 90 nm
1	Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera	A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LUT-based FPGA device, simple model circuit, ring oscillators, within-die variations, placement optimization, 90 nm
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto	Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Hidetoshi Onodera	Variability: Modeling and Its Impact on Design.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Akihiko Higuchi, Hidetoshi Onodera	A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Hidetoshi Onodera	Special Section on VLSI Design and CAD Algorithms.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera	A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.	FPL	2006	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Interconnect RL extraction at a single representative frequency.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera	Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera	Statistical Analysis of Clock Skew Variation in H-Tree Structure.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera	A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera	A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera	Successive Pad Assignment for Minimizing Supply Voltage Drop.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera	Effects of On-Chip Inductance on Power Distribution Grid.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera	Statistical Analysis of Clock Skew Variation in H-Tree Structure.	ISQED	2005	DBLP DOI BibTeX RDF
1	Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera	Effects of on-chip inductance on power distribution grid.	ISPD	2005	DBLP DOI BibTeX RDF	on-chip inductance, power supply noise, power distribution network, decoupling capacitance
1	Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera	A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera	Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera	Timing analysis considering temporal supply voltage fluctuation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Return path selection for loop RL extraction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera	Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Hidetoshi Onodera	A Comprehensive Simulation and Test Environment for Prototype VLSI Verification.	IEICE Transactions	2004	DBLP BibTeX RDF
1	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Equivalent waveform propagation for static timing analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera	Automatic Generation of Standard Cell Library in VDSM Technologies.	ISQED	2004	DBLP DOI BibTeX RDF
1	Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera	An SoC architecture and its design methodology using unifunctional heterogeneous processor array.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera	A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Representative frequency for interconnect R(f)L(f)C extraction.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera	RTL/ISS co-modeling methodology for embedded processor using SystemC.	ISCAS	2004	DBLP BibTeX RDF
1	Ken-ichi Okada, Hiroaki Hoshino, Hidetoshi Onodera	Modelling and optimization of on-chip spiral inductor in S-parameter domain.	ISCAS	2004	DBLP BibTeX RDF
1	Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera	Timing analysis considering spatial power/ground level variation.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Capturing crosstalk-induced waveform for accurate static timing analysis.	ISPD	2003	DBLP DOI BibTeX RDF	capacitive coupling noise, delay calculation, slope propagation, static timing analysis, crosstalk noise
1	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	Statistical modeling of gate-delay variation with consideration of intra-gate variability.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	A Statistical Gate-Delay Model Considering Intra-Gate Variability.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Equivalent Waveform Propagation for Static Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera	Crosstalk noise optimization by post-layout transistor sizing.	ISPD	2002	DBLP DOI BibTeX RDF	capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise
1	Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera	Experimental Study on Cell-Base High-Performance Datapath Design.	IWLS	2002	DBLP BibTeX RDF
1	Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera	A vector-pipeline DSP for low-rate videophones.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera	A dynamically phase adjusting PLL with a variable delay.	ASP-DAC	2001	DBLP DOI BibTeX RDF	phase adjust, variable delay, lock-up, PLL
1	Masanori Hashimoto, Hidetoshi Onodera	Post-layout transistor sizing for power reduction in cell-based design.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori	Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Hidetoshi Onodera	ST: PERL package for simulation and test environment.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera	Crosstalk Noise Estimation for Generic RC Trees.	ICCD	2001	DBLP BibTeX RDF
1	Masanori Hashimoto, Hidetoshi Onodera	A performance optimization method by gate sizing using statistical static timing analysis.	ISPD	2000	DBLP DOI BibTeX RDF
1	Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru	A method for linking process-level variability to system performances.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.	DAC	1999	DBLP DOI BibTeX RDF
1	Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru	Model-adaptable MOSFET parameter-extraction method using an intermediate model.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A power optimization method considering glitch reduction by gate sizing.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru	Proposal of a timing model for CMOS logic gates driving a CRC load.	ICCAD	1998	DBLP DOI BibTeX RDF
1	Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru	Timing and Power Optimization by Gate Sizing Considering False Paths.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
1	Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru	A model-adaptable MOSFET parameter extraction system.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru	An iterative gate sizing approach with accurate delay evaluation.	ICCAD	1995	DBLP DOI BibTeX RDF	delay evaluation, linear program, iteration, gate sizing
1	Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru	Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru	Branch-and-Bound Placement for Building Block Layout.	DAC	1991	DBLP DOI BibTeX RDF

Publications of "Hidetoshi Onodera" ( http://dblp.L3S.de/Authors/Hidetoshi_Onodera )