Search results for "Hiroki Matsutani"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano	Vertical Link On/Off Control Methods for Wireless 3-D NoCs.	ARCS	2012	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga	An Efficient Path Setup for a Hybrid Photonic Network-on-Chip.	IJNC	2011	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga	Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano	A vertical bubble flow network using inductive-coupling for 3-D CMPs.	NOCS	2011	DBLP BibTeX RDF
1	Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki	Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor.	RTCSA	2011	DBLP DOI BibTeX RDF
1	Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki	Design and Implementation of On-Chip Adaptive Router with Predictor for Regional Congestion.	RTCSA	2011	DBLP DOI BibTeX RDF
1	Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano	A Dynamic Link-Width Optimization for Network-on-Chip.	RTCSA	2011	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano	Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.	ICNC	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.	NOCS	2010	DBLP DOI BibTeX RDF	low power, Network-on-Chip, router, power gating
1	Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga	An Efficient Path Setup for a Photonic Network-on-Chip.	ICNC	2010	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks.	NAS	2010	DBLP DOI BibTeX RDF
1	Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching.	NAS	2010	DBLP DOI BibTeX RDF	non-minimal fully adaptive routing, NoC, deadlock-free routing, SAN, turn-model, virtual cut-through
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano	Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IEEE Trans. Parallel Distrib. Syst.	2009	DBLP DOI BibTeX RDF
1	Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano	MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.	FPL	2009	DBLP DOI BibTeX RDF
1	Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano	Evaluation of a multicore reconfigurable architecture with variable core sizes.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano	An on/off link activation method for low-power ethernet in PC clusters.	IPDPS	2009	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano	An On/Off Link Activation Method for Power Regulation in InfiniBand.	PDPTA	2009	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga	Prediction router: Yet another low latency on-chip router architecture.	HPCA	2009	DBLP DOI BibTeX RDF
1	José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano	Balanced Dimension-Order Routing for k-ary n-cubes.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi	A link removal methodology for Networks-on-Chip on reconfigurable systems.	FPL	2008	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston	A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, Network-on-Chip, routing algorithm, deadlock avoidance, on-chip network
1	Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano	Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF	low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang	Run-time power gating of on-chip routers using look-ahead routing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano	Three-Dimensional Layout of On-Chip Tree-Based Networks.	ISPAN	2008	DBLP DOI BibTeX RDF	Fat H-Tree, Network-on-Chip, Fat Tree, 3-D IC
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.	FPL	2007	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.	ICPP	2007	DBLP DOI BibTeX RDF
1	Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano	A Parametric Study of Scalable Interconnects on FPGAs.	ERSA	2006	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks.	ISCA PDCS	2006	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels.	ISPA	2006	DBLP DOI BibTeX RDF
1	Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima	An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.	FPT	2005	DBLP BibTeX RDF
1	Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai	Mobile Gateways for Mobile Ad-Hoc Networks with Network Mobility Support.	ICN	2005	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips.	PDPTA	2005	DBLP BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano	Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips.	ICPP Workshops	2005	DBLP DOI BibTeX RDF

Publications of "Hiroki Matsutani" ( http://dblp.L3S.de/Authors/Hiroki_Matsutani )