Search results for "Hiroshi Fuketa"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.	ISQED	2012	DBLP DOI BibTeX RDF
1	Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai	Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye	An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.	ISLPED	2011	DBLP BibTeX RDF
1	Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics.	ISLPED	2011	DBLP BibTeX RDF
1	Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates.	DAC	2011	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.	CICC	2009	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	layout, body bias

Publications of "Hiroshi Fuketa" ( http://dblp.L3S.de/Authors/Hiroshi_Fuketa )