Search results for "Hiroshi Nakamura"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura	Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating.	ISQED	2012	DBLP DOI BibTeX RDF
1	Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura	Stepwise sleep depth control for run-time leakage power saving.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura	A novel power-gating scheme utilizing data retentiveness on caches.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami	Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino (eds.)	Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011	ISLPED	2011	DBLP BibTeX RDF
1	Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura	On-chip detection methodology for break-even time of power gated function units.	ISLPED	2011	DBLP BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Array: A highly energy efficient reconfigurable accelerator.	FPT	2011	DBLP DOI BibTeX RDF
1	Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo	Geyser-2: The second prototype CPU with fine-grained run-time power gating.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Yutaka Ishikawa, Dong Tang, Hiroshi Nakamura (eds.)	16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010, Tokyo, Japan, December 13-15, 2010	PRDC	2010	DBLP BibTeX RDF
1	Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	Adaptive power gating for function units in a microprocessor.	ISQED	2010	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.	NOCS	2010	DBLP DOI BibTeX RDF	low power, Network-on-Chip, router, power gating
1	Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo	Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Satoshi Itoh, Yuetsu Kodama, Hiroshi Shimizu, Satoshi Sekiguchi, Hiroshi Nakamura, Naohiko Mori	Power consumption and efficiency of cooling in a Data Center.	GRID	2010	DBLP DOI BibTeX RDF
1	Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Takeshi Mishima, Hiroshi Nakamura	Pangea: An Eager Database Replication Middleware guaranteeing Snapshot Isolation without Modification of Database Servers.	PVLDB	2009	DBLP BibTeX RDF
1	Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Cooperative shared resource access control for low-power chip multiprocessors.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
1	Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura	Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, Hiroshi Nakamura	Power-performance modeling of heterogeneous cluster-based web servers.	GRID	2009	DBLP DOI BibTeX RDF
1	Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura	Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies.	PRDC	2008	DBLP DOI BibTeX RDF
1	Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura	Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values.	ICDM Workshops	2008	DBLP DOI BibTeX RDF
1	Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	A fine-grain dynamic sleep control scheme in MIPS R3000.	ICCD	2008	DBLP DOI BibTeX RDF
1	Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura	Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Takeshi Mishima, Hiroshi Nakamura	A Proposal of New Dependable Database Middleware with Consistency and Concurrency Control.	PRDC	2007	DBLP DOI BibTeX RDF	black box method, concurrency, dependability, consistency, database server
1	Masaaki Kondo, Yoshimichi Ikeda, Hiroshi Nakamura	A High Performance Cluster System Design by Adaptie Power Control.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Hiroshi Nakamura	Fast Abstracts.	DSN	2007	DBLP DOI BibTeX RDF
1	Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura	An intra-task dvfs technique based on statistical analysis of hardware events.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	statistical analysis, performance estimation, DVFS, hardware performance counters
1	Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya	Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.	DATE	2007	DBLP DOI BibTeX RDF
1	Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya	Power reduction of chip multi-processors using shared resource control cooperating with DVFS.	ICCD	2007	DBLP DOI BibTeX RDF
1	Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya	Design Method of High Performance and Low Power Functional Units Considering Delay Variations.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Energy-efficient dynamic instruction scheduling logic through instruction grouping.	ISLPED	2006	DBLP DOI BibTeX RDF	instruction grouping, issue queue, dynamic instruction scheduling
1	Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, Hiroshi Nakashima, Hiroshi Nakamura, Satoshi Matsuoka, Yoshihiko Hotta	MegaProto/E: power-aware high-performance cluster with commodity technology.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Kohji Itoh, Hiroshi Nakamura, Shunsuke Unno, Jun'ichi Kakegawa	A System Assisting Acquisition of Japanese Expressions Through Read-Write-Hear-Speaking and Comparing Between Use Cases of Relevant Expressions.	KES	2006	DBLP DOI BibTeX RDF
1	Daisuke Komura, Hiroshi Nakamura, Shuichi Tsutsumi, Hiroyuki Aburatani, Sigeo Ihara	Multidimensional support vector machines for visualization of gene expression data.	Bioinformatics	2005	DBLP DOI BibTeX RDF
1	Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, Yoshihiko Hotta	MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology.	SC	2005	DBLP DOI BibTeX RDF
1	Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Dynamic Instruction Cascading on GALS Microprocessors.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Ken-ichi Kurata, Hiroshi Nakamura, Vincent Breton	Secret sequence comparison on public grid computing resources.	CCGRID	2005	DBLP DOI BibTeX RDF
1	Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, Yoshihiko Hotta	MegaProto: A Low-Power and Compact Cluster for High-Performance Computing.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Chikafumi Takahashi, Mitsuhisa Sato, Daisuke Takahashi, Taisuke Boku, Hiroshi Nakamura, Masaaki Kondo, Motonobu Fujita	Empirical Study for Optimization of Power-Performance with On-Chip Memory.	ISHPC	2005	DBLP DOI BibTeX RDF
1	Masaaki Kondo, Hiroshi Nakamura	A Small, Fast and Low-Power Register File by Bit-Partitioning.	HPCA	2005	DBLP DOI BibTeX RDF
1	Nicolas Jacq, Christophe Blanchet, Christophe Combet, E. Cornillot, Laurent Duret, Ken-ichi Kurata, Hiroshi Nakamura, T. Silvestre, Vincent Breton	Grid as a bioinformatic tool.	Parallel Computing	2004	DBLP DOI BibTeX RDF
1	Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura	Data Movement Optimization for Software-Controlled On-Chip Memory.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
1	Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya	Skewed Checkpointing for Tolerating Multi-Node Failures.	SRDS	2004	DBLP DOI BibTeX RDF
1	Daisuke Komura, Hiroshi Nakamura, Shuichi Tsutsumi, Hiroyuki Aburatani, Sigeo Ihara	Multidimensional support vector machines for visualization of gene expression data.	SAC	2004	DBLP DOI BibTeX RDF	multidimensional Support Vecotor Machines, visualization, gene expression data, binary classification
1	Masaaki Kondo, Hiroshi Nakamura	Dynamic Processor Throttling for Power Efficient Computations.	PACS	2004	DBLP DOI BibTeX RDF
1	Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato	SCIMA-SMP: on-chip memory processor architecture for SMP.	WMPI	2004	DBLP DOI BibTeX RDF
1	Ken-ichi Kurata, Vincent Breton, Hiroshi Nakamura	A Method to Find Uniq e Sequences on Distrib ted Genomic Databases.	CCGRID	2003	DBLP DOI BibTeX RDF
1	Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya	Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya	Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units.	DATE	2003	DBLP DOI BibTeX RDF
1	Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya	A zero-time-overhead asynchronous four-phase controller.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya	Control signal sharing of asynchronous circuits using datapath delay information.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Masaaki Kondo, Motonobu Fujita, Hiroshi Nakamura	Software-controlled on-chip memory for high-performance and low-power computing.	SIGARCH Computer Architecture News	2002	DBLP DOI BibTeX RDF
1	Hiroshi Nakamura, Takanori Arai, Masahiro Fujita	Formal Verification of a Pipelined Processor with New Memory.	PRDC	2002	DBLP DOI BibTeX RDF
1	Ken-ichi Kurata, Christian Saguez, Gerald Dine, Hiroshi Nakamura	Rapid Analysis of Specificity of PCR Product on the Whole Genome.	PDPTA	2002	DBLP BibTeX RDF
1	T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura	Design and evaluation of high performance microprocessor with reconfigurable on-chip memory.	APCCAS	2002	DBLP DOI BibTeX RDF
1	Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya	Logic Optimization for Asynchronous SI Controllers using Transduction Method.	IWLS	2002	DBLP BibTeX RDF
1	Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura	Cache Line Impact on 3D PDE Solvers.	ISHPC	2002	DBLP BibTeX RDF
1	Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno	Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Hiroshi Nakamura	The standard SpecC language.	ISSS	2001	DBLP BibTeX RDF
1	Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku	Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
1	Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku	SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Kisaburo Nakazawa, Hiroshi Nakamura, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita	CP-PACS: A massively parallel processor at the University of Tsukuba.	Parallel Computing	1999	DBLP DOI BibTeX RDF
1	S. Aoki, R. Burkhalter, K. Kanaya, T. Yoshié, Taisuke Boku, Hiroshi Nakamura, Yoshiyuki Yamashita	Performance of lattice QCD programs on CP-PACS.	Parallel Computing	1999	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau	Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	data cache, Loop tiling, data alignment, cache conflict
1	Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau	Improving cache Performance Through Tiling and Data Alignment.	IRREGULAR	1997	DBLP DOI BibTeX RDF
1	Taisuke Boku, Ken'ichi Itakura, Hiroshi Nakamura, Kisaburo Nakazawa	CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations.	International Conference on Supercomputing	1997	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau	A Data Alignment Technique for Improving Cache Performance.	ICCD	1997	DBLP BibTeX RDF
1	Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita	Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers.	HICSS	1994	DBLP BibTeX RDF
1	Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita	A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF
1	Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe	Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline.	SC	1992	DBLP BibTeX RDF
1	Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka	A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio.	CAV	1990	DBLP DOI BibTeX RDF
1	Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka	Logic Design Assistence Using Temporal Logic Based Language Tokio.	LP	1989	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka	Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis.	LP	1985	DBLP DOI BibTeX RDF

Publications of "Hiroshi Nakamura" ( http://dblp.L3S.de/Authors/Hiroshi_Nakamura )