Search results for "Hong Wang 0003"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Hong Jiang, Guei-Yuan Lueh, Thomas Piazza, Hong Wang 0003	Bothnia: a dual-personality extension to the Intel integrated graphics driver.	Operating Systems Review	2011	DBLP DOI BibTeX RDF
1	Guilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang 0003	AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
1	Sung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra	BLoG: post-silicon bug localization in processors using bug localization graphs.	DAC	2010	DBLP DOI BibTeX RDF	IFRA, BLoG, silicon debug, post-silicon validation
1	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
1	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
1	Samantika Subramaniam, Anne Bracy, Hong Wang 0003, Gabriel H. Loh	Criticality-based optimizations for efficient load processing.	HPCA	2009	DBLP DOI BibTeX RDF
1	Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang 0003, John Paul Shen	Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF	Speculative thread level parallelism, pre-computation slices, thread partitioning, multi-core architecture
1	Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang 0003, Mark Horowitz	Processor Performance Modeling using Symbolic Simulation.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003	Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.	PACT	2008	DBLP DOI BibTeX RDF	ia32, on-chip integration, chip multiprocessor, heterogeneous
1	Michael D. Linderman, Jamison D. Collins, Hong Wang 0003, Teresa H. Y. Meng	Merge: a programming model for heterogeneous multi-core systems.	ASPLOS	2008	DBLP DOI BibTeX RDF	GPGPU, predicate dispatch, heterogeneous multi-core
1	Benjamin C. Lee, Jamison D. Collins, Hong Wang 0003, David Brooks	CPR: Composable performance regression for scalable multiprocessor models.	MICRO	2008	DBLP DOI BibTeX RDF
1	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003	EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.	PLDI	2007	DBLP DOI BibTeX RDF	GPU, openMP, heterogeneous multi-cores
1	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang 0003	Sequencer virtualization.	ICS	2007	DBLP DOI BibTeX RDF	virtualization, multi-cores, MIMD
1	Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang 0003, John Paul Shen	Multiple Instruction Stream Processor.	ISCA	2006	DBLP DOI BibTeX RDF
1	Satish Narayanasamy, Hong Wang 0003, Perry H. Wang, John Paul Shen, Brad Calder	A Dependency Chain Clustered Microarchitecture.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen	Helper Threads via Virtual Multithreading.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang 0003, Donald Yeung, Milind Girkar, John Paul Shen	Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors.	CGO	2004	DBLP DOI BibTeX RDF
1	Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen	Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform.	ASPLOS	2004	DBLP DOI BibTeX RDF	DB2 database, cache miss prefetching, itanium processor, switch-on-event, multithreading, helper thread, PAL
1	Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003	Control Flow Optimization Via Dynamic Reconvergence Prediction.	MICRO	2004	DBLP DOI BibTeX RDF
1	Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang 0003, John Paul Shen	Hardware Support for Prescient Instruction Prefetch.	HPCA	2004	DBLP DOI BibTeX RDF
1	Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang 0003	Best of Both Latency and Throughput.	ICCD	2004	DBLP DOI BibTeX RDF
1	Hong Wang 0003, Shiri Manor, Dave LaFollette, Nadav Nesher, Ku-jei King, Perry H. Wang, Shay Levy, Shai Satt, Gal Carmeli, Arjun Kapur, Ioannis Schoinas, Ed Rubinstein, Rahul Bhatt	Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations.	ISPASS	2003	DBLP DOI BibTeX RDF
1	Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang 0003, John Paul Shen	A framework for modeling and optimization of prescient instruction prefetch.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	optimization, multithreading, analytical modeling, path expressions, helper threads, instruction prefetch
1	Shih-Wei Liao, Perry H. Wang, Hong Wang 0003, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery	Post-Pass Binary Adaptation for Software-Based Speculative Precomputation.	PLDI	2002	DBLP DOI BibTeX RDF	chaining speculative precomputation, dependence reduction, long-range thread-based prefetching, loop rotation, post-pass, scheduling, prediction, slicing, speculation, triggering, pointer, slack, delay minimization
1	R. David Weldon, Steven S. Chang, Hong Wang 0003, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen	Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF
1	Perry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen	Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation.	HPCA	2002	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Hong Wang 0003, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen	Speculative precomputation: long-range prefetching of delinquent loads.	ISCA	2001	DBLP DOI BibTeX RDF	Systems Application Architecture
1	Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003, John Paul Shen	Dynamic speculative precomputation.	MICRO	2001	DBLP DOI BibTeX RDF
1	Perry H. Wang, Hong Wang 0003, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen	Register Renaming and Scheduling for Dynamic Execution of Predicated Code.	HPCA	2001	DBLP DOI BibTeX RDF
1	Thomas Y. Yeh, Hong Wang 0003	Redundant Arithmetic Optimizations (Research Note).	Euro-Par	2000	DBLP DOI BibTeX RDF
1	Hong Wang 0003, Tong Sun, Qing Yang	Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF
1	Hong Wang 0003, Tong Sun, Qing Yang	CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches.	ISCA	1995	DBLP DOI BibTeX RDF
1	Qing Yang, Hong Wang 0003	A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	graph approach, minimizing processor fragmentation, primecube graph, simulation, performance evaluation, multiprocessing systems, hypercube networks, digital simulation, hypercube multiprocessors
1	Qing Yang, Hong Wang 0003	On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers.	ICPP	1992	DBLP BibTeX RDF
1	Hong Wang 0003, Qing Yang	Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors.	ICPP	1991	DBLP BibTeX RDF

Publications of "Hong Wang 0003" ( http://dblp.L3S.de/Authors/Hong_Wang_0003 )