Search results for "Houman Homayoun"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Houman Homayoun, Mehryar Rahmatian, Vasileios Kontorinis, Shahin Golshan, Dean M. Tullsen	Hot peripheral thermal management to mitigate cache temperature variation.	ISQED	2012	DBLP DOI BibTeX RDF
1	Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi Kudahi	History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.	ISQED	2012	DBLP DOI BibTeX RDF
1	Houman Homayoun, Vasileios Kontorinis, Amirali Shayan, Ta-Wei Lin, Dean M. Tullsen	Dynamically heterogeneous cores through 3D resource pooling.	HPCA	2012	DBLP DOI BibTeX RDF
1	Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum	Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari	MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Abbas BanaiyanMofrad, Houman Homayoun, Nikil Dutt	FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation.	CASES	2011	DBLP DOI BibTeX RDF
1	Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi	Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.	ISQED	2010	DBLP DOI BibTeX RDF
1	Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum	Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.	ISLPED	2010	DBLP DOI BibTeX RDF	computer aided design, placement, dynamic reconfiguration, temperature, reconfigurable systems
1	Arup Chakraborty, Houman Homayoun, Amin Khajeh, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi	E < MC2: less energy through multi-copy cache.	CASES	2010	DBLP DOI BibTeX RDF
1	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
1	Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt	RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).	CASES	2009	DBLP DOI BibTeX RDF	low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs
1	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling.	DATE	2009	DBLP BibTeX RDF
1	Houman Homayoun, Mohammad A. Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum	A centralized cache miss driven technique to improve processor power dissipation.	ICSAMOS	2008	DBLP DOI BibTeX RDF
1	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.	DAC	2008	DBLP DOI BibTeX RDF	dynamic resizing, performance, embedded processor, register file
1	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.	CASES	2008	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power
1	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.	ICCD	2008	DBLP DOI BibTeX RDF
1	Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot	Adaptive techniques for leakage power management in L2 cache peripheral circuits.	ICCD	2008	DBLP DOI BibTeX RDF
1	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.	LCTES	2008	DBLP DOI BibTeX RDF	energy-delay, out-of-order embedded processor, resource resizing, performance, architecture
1	Houman Homayoun, Alexander V. Veidenbaum	Reducing leakage power in peripheral circuits of L2 caches.	ICCD	2007	DBLP DOI BibTeX RDF
1	Houman Homayoun, Amirali Baniasadi	Reducing Execution Unit Leakage Power in Embedded Processors.	SAMOS	2006	DBLP DOI BibTeX RDF
1	Houman Homayoun, Ted H. Szymanski	Reducing the Instruction Queue Leakage Power in Superscalar Processors.	CCECE	2006	DBLP DOI BibTeX RDF

Publications of "Houman Homayoun" ( http://dblp.L3S.de/Authors/Houman_Homayoun )