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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 21 publication records. Showing 21 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hritam Dutta |
Synthesis and exploration of loop accelerators for systems-on-a-chip.  |
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2011 |
RDF |
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| 1 | Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert |
Modeling and synthesis of communication subsystems for loop accelerator pipelines.  |
ASAP  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier |
A holistic approach for tightly coupled reconfigurable parallel processors.  |
Microprocessors and Microsystems - Embedded Hardware Design  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich |
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.  |
SAMOS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Hritam Dutta, Frank Hannig, Jürgen Teich |
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.  |
ARCS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Frank Hannig, Hritam Dutta, Jürgen Teich |
Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.  |
ARCS  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich |
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.  |
ASAP  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich |
Impact of Loop Tiling on the Controller Logic of Acceleration Engines.  |
ASAP  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich |
Model-based synthesis and optimization of static multi-rate image processing algorithms.  |
DATE  |
2009 |
DBLP BibTeX RDF |
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| 1 | Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner |
Coarse-grained reconfiguration.  |
FPL  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich |
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.  |
ARC  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich |
Efficient control generation for mapping nested loop programs onto processor arrays.  |
Journal of Systems Architecture  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet |
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.  |
ERSA  |
2007 |
DBLP BibTeX RDF |
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| 1 | Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier |
Massively Parallel Processor Architectures: A Co-design Approach.  |
ReCoSoC  |
2007 |
DBLP BibTeX RDF |
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| 1 | Frank Hannig, Hritam Dutta, Jürgen Teich |
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology.  |
IJES  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Hritam Dutta, Frank Hannig, Jürgen Teich |
Controller Synthesis for Mapping Partitioned Programs on Array Architectures.  |
ARCS  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Hritam Dutta, Frank Hannig, Jürgen Teich |
Hierarchical Partitioning for Piecewise Linear Algorithms.  |
PARELEC  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger |
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.  |
ASAP  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich |
Automatic FIR Filter Generation for FPGAs.  |
SAMOS  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys |
Co-Design of Massively Parallel Embedded Processor Architectures.  |
ReCoSoC  |
2005 |
DBLP BibTeX RDF |
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| 1 | Frank Hannig, Hritam Dutta, Jürgen Teich |
Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology.  |
IPDPS  |
2004 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #21 of 21 (100 per page; Change: )
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