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Publications of "Hritam Dutta" ( http://dblp.L3S.de/Authors/Hritam_Dutta )

  Author page on DBLP  Author page in RDF  Community of Hritam Dutta in ASPL-2

Publication years (Num. hits)
2004-2009 (19) 2010-2011 (2)
Publication types (Num. hits)
article(3) inproceedings(17) phdthesis(1)
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Found 21 publication records. Showing 21 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Hritam Dutta Synthesis and exploration of loop accelerators for systems-on-a-chip. Search on Bibsonomy 2011   RDF
1Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert Modeling and synthesis of communication subsystems for loop accelerator pipelines. Search on Bibsonomy ASAP The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier A holistic approach for tightly coupled reconfigurable parallel processors. Search on Bibsonomy Microprocessors and Microsystems - Embedded Hardware Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. Search on Bibsonomy SAMOS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Hritam Dutta, Frank Hannig, Jürgen Teich Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. Search on Bibsonomy ARCS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Frank Hannig, Hritam Dutta, Jürgen Teich Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. Search on Bibsonomy ARCS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. Search on Bibsonomy ASAP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich Impact of Loop Tiling on the Controller Logic of Acceleration Engines. Search on Bibsonomy ASAP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich Model-based synthesis and optimization of static multi-rate image processing algorithms. Search on Bibsonomy DATE The full citation details ... 2009 DBLP  BibTeX  RDF
1Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner Coarse-grained reconfiguration. Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. Search on Bibsonomy ARC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich Efficient control generation for mapping nested loop programs onto processor arrays. Search on Bibsonomy Journal of Systems Architecture The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. Search on Bibsonomy ERSA The full citation details ... 2007 DBLP  BibTeX  RDF
1Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier Massively Parallel Processor Architectures: A Co-design Approach. Search on Bibsonomy ReCoSoC The full citation details ... 2007 DBLP  BibTeX  RDF
1Frank Hannig, Hritam Dutta, Jürgen Teich Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. Search on Bibsonomy IJES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Hritam Dutta, Frank Hannig, Jürgen Teich Controller Synthesis for Mapping Partitioned Programs on Array Architectures. Search on Bibsonomy ARCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Hritam Dutta, Frank Hannig, Jürgen Teich Hierarchical Partitioning for Piecewise Linear Algorithms. Search on Bibsonomy PARELEC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. Search on Bibsonomy ASAP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich Automatic FIR Filter Generation for FPGAs. Search on Bibsonomy SAMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys Co-Design of Massively Parallel Embedded Processor Architectures. Search on Bibsonomy ReCoSoC The full citation details ... 2005 DBLP  BibTeX  RDF
1Frank Hannig, Hritam Dutta, Jürgen Teich Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. Search on Bibsonomy IPDPS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
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