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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18 occurrences of 9 keywords
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Results
Found 13 publication records. Showing 13 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yongjun Park, Sangwon Seo, Hyunchul Park, Hyoun Kyu Cho, Scott A. Mahlke |
SIMD defragmenter: efficient ILP realization on data-parallel architectures.  |
ASPLOS  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Hyunchul Park, Dongkun Shin |
Buffer flush and address mapping scheme for flash memory solid-state disk. |
Journal of Systems Architecture - Embedded Systems Design |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Yongjun Park, Hyunchul Park, Scott A. Mahlke, Sukjin Kim |
Resource recycling: putting idle resources to work on a composable accelerator. |
CASES |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Hyunchul Park, Yongjun Park, Scott A. Mahlke |
Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
programmable accelerator, virtualization, software pipelining |
| 1 | Yongjun Park, Hyunchul Park, Scott A. Mahlke |
CGRA express: accelerating execution using dynamic operation fusion. |
CASES |
2009 |
DBLP DOI BibTeX RDF |
latency-constrained, subgraph accelerator, modulo scheduling, coarse-grained reconfigurable architecture |
| 1 | Hyunchul Park, Yongjun Park, Scott A. Mahlke |
A dataflow-centric approach to design low power control paths in CGRAs. |
SASP |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Taewook Oh, Bernhard Egger, Hyunchul Park, Scott A. Mahlke |
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures. |
LCTES |
2009 |
DBLP DOI BibTeX RDF |
software pipelining, placement and routing, coarse-grained reconfigurable architectures |
| 1 | Kevin Fan, Hyunchul Park, Manjunath Kudlur, Scott A. Mahlke |
Modulo scheduling for highly customized datapaths to increase hardware reusability. |
CGO |
2008 |
DBLP DOI BibTeX RDF |
programmable asic, modulo scheduling, loop accelerator |
| 1 | Hyunchul Park, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-seok Kim |
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. |
PACT |
2008 |
DBLP DOI BibTeX RDF |
operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture |
| 1 | Hyunchul Park, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke |
Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures. |
CASES |
2006 |
DBLP DOI BibTeX RDF |
graph embedding, modulo scheduling, coarse-grained reconfigurable architecture |
| 1 | Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke |
Increasing hardware efficiency with multifunction loop accelerators. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware |
| 1 | Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke |
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Nathan Clark, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke, Krisztián Flautner |
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization. |
MICRO |
2004 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #13 of 13 (100 per page; Change: )
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