Search results for "IDDQ"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen	Is IDDQ testing not applicable for deep submicron VLSI in year 2011?	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	deep submicron VLSI, IDDQ current estimation, random process deviations, IDDQ distributions, VLSI, statistical analysis, integrated circuit testing, CMOS integrated circuits, leakage currents, IDDQ testing, statistical approach, standard deviation, input vectors, circuit size
4	Sagar S. Sabade, D. M. H. Walker	Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification.	VLSI Design	2003	DBLP DOI BibTeX RDF	spatial correlation, IDDQ testing, delta IDDQ
4	Srdjan Dragic, Martin Margala	A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test.	ISVLSI	2002	DBLP DOI BibTeX RDF	Current Amplifier, On-Line Testing, Iddq, delta Iddq, Current Monitoring
4	Paul Lee, Alfred Chen, Dilip Mathew	A Speed-Dependent Approach for Delta IDDQ Implementation. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	Self-scaling IDDQ, Speed Performance Index, characterization, Delta IDDQ
4	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita	Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	IDDQ measurement vector, sequential circuit, bridging fault, IDDQ testing
4	Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita	A high-speed IDDQ sensor implementation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit feedback, high-speed IDDQ sensor implementation, submicron CMOS process, feedback scheme, floppy-disk controller IDDQ test, current sensor, built-in sensor, 0.35 micron, 50 MHz, integrated circuit testing, CMOS digital integrated circuits, BICS, electric current measurement, electric sensing devices
4	B. Straka, Hans A. R. Manhaeve, Jozef Vanneuville, M. Svajda	A Fully Digital Controlled Off-Chip IDDQ Measurement Unit.	DATE	1998	DBLP DOI BibTeX RDF	IDDQ monitors, test hardware, CMOS, testability, integrated circuits, IDDQ
4	Hisashi Kondo, Kwang-Ting Cheng	An Efficient Compact Test Generator for IDDQ Testing.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Selective IDDQ, Pattern Compaction, Pseudo Stuck-at Fault, Essential Fault, Test, ATPG, Fault Model, Testability, IDDQ, Leakage Fault
4	Masaru Sanada	A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq.	VTS	1996	DBLP DOI BibTeX RDF	CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration
4	Hisashi Kondo, Kwang-Ting Cheng	Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	Selective IDDQ, Pseudo Stuck-at Fault, Sequential ATPG, Vector compaction, Test, Fault model, IDDQ, Leakage Fault
3	Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel	Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	Quiescent Signal Analysis, defect detection, IDDQ
3	Chuen-Song Chen, Jien-Chung Lo, Tian Xia	An indirect current sensing technique for IDDQ and IDDT tests.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	IDDT, IDDQ, current testing, BICS
3	Ashutosh Sharma, Anura P. Jayasumana, Yashwant K. Malaiya	X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data.	VTS	2006	DBLP DOI BibTeX RDF	Defect Correlation, Principal Component Analysis, IDDQ, Binning, Test Optimization
3	Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni	An Embedded IDDQ Testing Architecture and Technique.	ISQED	2003	DBLP DOI BibTeX RDF	IEEE 1149.1, Design for Testability (DFT), Boundary Scan, IDDQ Testing
3	Sagar S. Sabade, D. M. H. Walker	Use of Multiple IDDQ Test Metrics for Outlier Identification.	VTS	2003	DBLP DOI BibTeX RDF	Current ratio, neighbor current ratio, outlier identification, spatial correlation, IDDQ testing
3	Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen	Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	VLSI, IDDQ testing, deep sub-micron
3	Toshiyuki Maeda, Kozo Kinoshita	Compaction of IDDQ Test Sequence Using Reassignment Method.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	reassignment method, weighted random vector, sequential circuit, IDDQ testing, test compaction
3	Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda	High speed IDDQ test and its testability for process variation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing
3	Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi	Cyclic greedy generation method for limited number of IDDQ tests.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	cyclic greedy generation method, undetected faults, ISCAS85Y circuits, short circuit faults, fault diagnosis, integrated circuit testing, iterative methods, iterative method, CMOS integrated circuits, IDDQ tests, test patterns, CMOS IC, electric current measurement, cyclic, random patterns
3	Claude Thibeault	Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm.	VTS	2000	DBLP DOI BibTeX RDF	probabilistic signatures, double faults, Diagnosis, Viterbi algorithm, Delta Iddq
3	Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce	Delta Iddq for Testing Reliability.	VTS	2000	DBLP DOI BibTeX RDF	reliability, Iddq
3	Hugo Cheung, Sandeep K. Gupta	A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study.	VTS	2000	DBLP DOI BibTeX RDF	critical severity, test escape, fault modeling, IDDQ, yield loss
3	Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos	A Compact Built-In Current Sensor for IDDQ Testing.	IOLTW	2000	DBLP DOI BibTeX RDF	Bridging and Stuck-on fault testability, Design for testability, DFT, IDDQ testing, Built in current sensors, BICS, Current monitoring
3	Víctor H. Champac, José Castillejos, Joan Figueras	IDDQ Testing of Opens in CMOS SRAMs.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	data retention faults, memory testing, opens, IDDQ
3	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita	Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential circuit, fault simulation, bridging fault, IDDQ testing
3	Arabi Keshk, Kozo Kinoshita, Yukiya Miura	IDDQ Current Dependency on Test Vectors and Bridging Resistance.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Bridging fault, IDDQ Testing
3	Tsuyoshi Shinogi, Terumine Hayashi	A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	compact test generation, parallel processing, ATPG, IDDQ testing
3	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	IDDQ testing, test compaction
3	Yinghua Min, Zhongcheng Li	IDDT Testing versus IDDQ Testing.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	IDDT test, IDDQ test, stuck-open fault, Boolean process
3	Rosa Rodríguez-Montañés, Joan Figueras	Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.	DATE	1998	DBLP DOI BibTeX RDF	IDDQ testability, CMOS, deep-submicron
3	Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken	An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.	VTS	1997	DBLP DOI BibTeX RDF	semiconductor testing, stuck-fault testing, ASIC device, application specific integrated circuits, functional testing, IDDQ testing, delay-fault testing, scan testing
3	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
3	Peter C. Maxwell	The use of IDDQ testing in low stuck-at coverage situations.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at coverage situations, quality goal, graded coverage, composite metric, fault diagnosis, logic testing, logic tests, integrated circuit testing, automatic testing, application specific integrated circuits, ASIC, CMOS logic circuits, IDDQ testing, IC testing
3	Jason P. Hurst, Adit D. Singh	A differential built-in current sensor design for high speed IDDQ testing.	VLSI Design	1995	DBLP DOI BibTeX RDF	built-in current sensor design, high speed IDDQ testing, differential architecture, quiescent current detection, BIST environment, n-well technology, MOSIS, 31.25 MHz, VLSI, built-in self test, built-in self-test, integrated circuit testing, design for testability, integrated circuit design, CMOS digital integrated circuits, electric current measurement, 2 micron, electric sensing devices
2	Josep Rius, Luis Elvira Villagra, Maurice Meijer	A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits.	European Test Symposium	2009	DBLP DOI BibTeX RDF	IDDQ testing
2	B. Straka, Hans A. R. Manhaeve, J. Brenkus, Stefaan Kerckenaere	Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality.	DATE	2008	DBLP DOI BibTeX RDF
2	Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková	Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology.	DDECS	2008	DBLP DOI BibTeX RDF
2	Jan Schat	Evaluation of the Iddq Signature in devices with Gauss-distributed background current.	DDECS	2008	DBLP DOI BibTeX RDF
2	Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy	Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.	DAC	2007	DBLP DOI BibTeX RDF
2	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
2	Chuen-Song Chen, Jien-Chung Lo, Tian Xia	Equivalent IDDQ Tests for Systems with Regulated Power Supply.	DFT	2006	DBLP DOI BibTeX RDF
2	Abhishek Singh, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel	Defect Simulation Methodology for iDDT Testing.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test
2	Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka	IDDQ Testing Method using a Scan Pattern for Production Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Bin Xue, D. M. H. Walker	Is IDDQ Test of Microprocessors Feasible?	MTV	2005	DBLP DOI BibTeX RDF
2	Scott Davidson	Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	X-tolerant, IC outlier, ATPG, BIST, yield, IDDQ, International Test Conference, test metrics
2	Chintan Patel, Abhishek Singh, Jim Plusquellic	Defect Detection Using Quiescent Signal Analysis.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	multiple current measurements, Quiescent Signal Analysis, IDDQ, current testing, defect-based testing, parametric testing
2	Phil Nigh, Anne E. Gattiker	Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions.	ITC	2004	DBLP DOI BibTeX RDF
2	Chintan Patel, Abhishek Singh, Jim Plusquellic	Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement.	ITC	2004	DBLP DOI BibTeX RDF
2	Sagar S. Sabade, D. M. H. Walker	Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Sagar S. Sabade, D. M. H. Walker	IDDX-based test methods: A survey.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	IDDT test, test, VLSI testing, IDDQ
2	Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning	Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ.	ITC	2003	DBLP DOI BibTeX RDF
2	Yukio Okuda, Nobuyuki Furukawa	Hysteresis of Intrinsic IDDQ Currents.	ITC	2003	DBLP DOI BibTeX RDF
2	Nobuhiro Sato, Yoshihiro Hashimoto	A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation.	ITC	2003	DBLP DOI BibTeX RDF
2	Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota	Test Vector Generation Based on Correlation Model for Ratio-Iddq.	ITC	2003	DBLP DOI BibTeX RDF
2	Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita	A BIST Circuit for IDDQ Tests.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
2	Thomas J. Vogels	Effectiveness of I-V Testing in Comparison to IDDq Tests.	VTS	2003	DBLP DOI BibTeX RDF
2	Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal	New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.	VLSI Design	2003	DBLP DOI BibTeX RDF
2	Abhijit Prasad, D. M. H. Walker	Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors.	DFT	2003	DBLP DOI BibTeX RDF
2	W. Robert Daasch, James McNames, Robert Madge, Kevin Cota	Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
2	Sagar S. Sabade, D. M. H. Walker	IDDQ Test: Will It Survive the DSM Challenge?	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
2	Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni	Extending the Viability of IDDQ Testing in the Deep Submicron Era. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
2	Bram Kruseman, Stefan van den Oetelaar, Josep Rius	Comparison of IDDQ Testing and Very-Low Voltage Testing.	ITC	2002	DBLP DOI BibTeX RDF
2	W. Robert Daasch, Kevin Cota, James McNames, Robert Madge	Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data.	ITC	2002	DBLP DOI BibTeX RDF
2	David I. Bergman, Hans Engler	Improved IDDQ Testing with Empirical Linear Prediction.	ITC	2002	DBLP DOI BibTeX RDF
2	Swarup Bhunia, Hai Li, Kaushik Roy	A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Yukio Okuda	Eigen-Signatures for Regularity-based IDDQ Testing.	VTS	2002	DBLP DOI BibTeX RDF
2	Claude Thibeault	Speeding-Up IDDQ Measurements.	VTS	2002	DBLP DOI BibTeX RDF
2	Sagar S. Sabade, D. M. H. Walker	Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction.	VTS	2002	DBLP DOI BibTeX RDF
2	Sagar S. Sabade, D. M. H. Walker	Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	C. P. Ravikumar, Rahul Kumar	Divide-and-Conquer IDDQ Testing for Core-Based System Chips.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz	CMOS Standard Cells Characterization for IDDQ Testing. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
2	Sagar S. Sabade, D. M. H. Walker	Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
2	Yukiya Miura, Shuichi Seno	Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis
2	Zhanping Chen, Liqiong Wei, Kaushik Roy	On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita	IDDQ Sensing Technique for High Speed IDDQ Testing.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
2	Chintan Patel, Jim Plusquellic	A Process and Technology-Tolerant IDDQ Method for IC Diagnosis.	VTS	2001	DBLP DOI BibTeX RDF
2	Anton Chichkov, Dirk Merlier, Peter Cox	Current Testing Procedure for Deep Submicron Devices.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	ASIC testing, IDDQ, deep submicron
2	Antonio Zenteno, Víctor H. Champac, Joan Figueras	Detectability Conditions of Full Opens in the Interconnections.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	logic testing, IDDQ testing, opens, defect modeling
2	Sreejit Chakravarty, Sujit T. Zachariah	STBM: a fast algorithm to simulate IDDQ tests forleakage faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
2	Alessandro Bogliolo, Michele Favalli, Maurizio Damiani	Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Zhanping Chen, Liqiong Wei, Kaushik Roy	On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.	ISQED	2000	DBLP DOI BibTeX RDF
2	Sri Jandhyala, Hari Balachandran, Manidip Sengupta, Anura P. Jayasumana	Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs.	VTS	2000	DBLP DOI BibTeX RDF
2	Juan M. Díez, Juan Carlos López	Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion.	DATE	2000	DBLP DOI BibTeX RDF
2	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda	Testability Analysis of IDDQ Testing with Large Threshold Value. (PDF / PS)	DFT	2000	DBLP DOI BibTeX RDF
2	Shengli Li, Kai Zhang, Jien-Chung Lo	The 2nd Order Analysis of IDDQ Test Data. (PDF / PS)	DFT	2000	DBLP DOI BibTeX RDF
2	Martin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková	I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test.	IOLTW	2000	DBLP DOI BibTeX RDF	VLSI, Testing, Sensors, Iddq, Ultra-Low-Voltage, Current
2	Manoj Sachdev, Hans G. Kerkhoff	Configurations for IDDQ-Testable PLAs.	IEEE Design & Test of Computers	1999	DBLP DOI BibTeX RDF
2	Junichi Hirase, Naoki Shindou, Kouji Akahori	Scan Chain Diagnosis Using IDDQ Current Measurement.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
2	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
2	Claude Thibeault	On the Comparison of IDDQ and IDDQ Testing.	VTS	1999	DBLP DOI BibTeX RDF
2	Robert C. Aitken	Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage.	VTS	1999	DBLP DOI BibTeX RDF
2	Th. Calin, Lorena Anghel, Michael Nicolaidis	Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS.	VTS	1999	DBLP DOI BibTeX RDF
2	R. D. (Shawn) Blanton	IDDQ-Testability of Tree Circuits.	VLSI Design	1999	DBLP DOI BibTeX RDF
2	Josep Rius, Joan Figueras	Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.	DATE	1999	DBLP DOI BibTeX RDF
2	K. Raahernifar, M. Ahmadi	On-line IDDQ fault testing for CMOS/BiCMOS logic families.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Yukiya Miura, Hiroshi Yamazaki	A Low-Loss Built-In Current Sensor.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	low-voltage LSIs, multiple power supplies, IDDQ testing, Built-in current sensor
2	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
2	Eberhard Böhl, Thomas Lindenkreuz, Matthias Meerwein	On-Chip IDDQ Testing in the AE11 Fail-Stop Controller.	IEEE Design & Test of Computers	1998	DBLP DOI BibTeX RDF
2	Anne E. Gattiker, Wojciech Maly	Toward understanding "Iddq-only" fails.	ITC	1998	DBLP DOI BibTeX RDF
2	Claude Thibeault, Luc Boisvert	Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results.	ITC	1998	DBLP DOI BibTeX RDF