Search results for "IEEE Micro"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	C. Kevin Shum, Fadi Busaba, Christian Jacobi	IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	Erik R. Altman	Hot Chips and the Incomplete Job of Exploiting Them.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Sriram R. Vangal	IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	Richard Mateosian	Ethics of Big Data.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	Shane Greenstein	The Online Honesty Box.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David Blaauw, Trevor N. Mudge	Centip3De: A 64-Core, 3D Stacked Near-Threshold System.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	Christos Kozyrakis, Rumi Zahir	Selected Research from Hot Chips 24.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	John R. Feehrer, Sumti Jairath, Paul Loewenstein, Ram Sivaramakrishnan, David Smentek, Sebastian Turullols, Ali Vahidsafa	The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	Robert Rogenmoser, Lawrence T. Clark	Reducing Transistor Variability for High Performance Low Power Chips.	IEEE Micro	2013	DBLP DOI BibTeX RDF
1	Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu	A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Venkatraman Govindaraju, Chen-Han Ho, Tony Nowatzki, Jatin Chhugani, Nadathur Satish, Karthikeyan Sankaralingam, Changkyu Kim	DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn	Optical High Radix Switch Design.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Sherief Reda, Ryan Cochran, Ayse Kivilcim Coskun	Adaptive Power Capping for Servers with Multithreaded Workloads.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Dong Chen, Noel Eisley, Philip Heidelberger, Robert M. Senger, Yutaka Sugawara, Sameer Kumar 0001, Valentina Salapura, David L. Satterfield, Burkhard D. Steinmacher-Burow, Jeffrey J. Parker	The IBM Blue Gene/Q Interconnection Fabric.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Ruud A. Haring, Martin Ohmacht, Thomas Fox, Michael Gschwind, David L. Satterfield, Krishnan Sugavanam, Paul Coteus, Philip Heidelberger, Matthias A. Blumrich, Robert W. Wisniewski, Alan Gara, George L.-T. Chiu, Peter A. Boyle, Norman H. Christ, Changhoan Kim	The IBM Blue Gene/Q Compute Chip.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Shane Greenstein	A Big Payoff.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Parthasarathy Ranganathan, Jichuan Chang	(Re)Designing Data-Centric Data Centers.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Manish Shah, Robert T. Golla, Greg Grohoski, Paul J. Jordan, Jama Barreh, Jeffrey Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Thomas A. Ziaja	Sparc T4: A Dynamically Threaded Server-on-a-Chip.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Paolo Faraboschi, T. N. Vijaykumar	Top Picks from the 2011 Computer Architecture Conferences.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Erik R. Altman	Power- and Energy-Aware Computing.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Efraim Rotem, Alon Naveh, Avinash Ananthakrishnan, Eliezer Weissmann, Doron Rajwan	Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	David I. August	Parallelizing Sequential Code.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Richard Mateosian	Forewords by Celebrities.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Shane Greenstein	Calm Economics.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez	Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Richard Mateosian	Miscellany.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Yuichiro Ajima, Tomohiro Inoue, Shinya Hiramoto, Yuzo Takagi, Toshiyuki Shimizu	The Tofu Interconnect.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Erik R. Altman	Micro Evolution.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Kazutoshi Suito, Rikuhei Ueda, Kei Fujii, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki	The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Jinwook Oh, Gyeonghoon Kim, Injoon Hong, Junyoung Park, Seungjin Lee, Joo-Young Kim, Jeong-Ho Woo, Hoi-Jun Yoo	Low-Power, Real-Time Object-Recognition Processors for Mobile Vision Systems.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Mark D. Hill	Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Josep Torrellas	2012 International Symposium on Computer Architecture Influential Paper Award.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Shane Greenstein	The Prevailing View.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Dongrui Fan, Hao Zhang, Da Wang, Xiaochun Ye, Fenglong Song, Guojie Li, Ninghui Sun	Godson-T: An Efficient Many-Core Processor Exploring Thread-Level Parallelism.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Michael C. Doggett	Texture Caches.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Hadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, Doug Burger	Dark Silicon and the End of Multicore Scaling.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	David Burgess, Edmund Gieske, James Holt, Thomas Hoy, Gary Whisenhunt	e6500: Freescale's Low-Power, High-Performance Multithreaded Embedded Processor.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Allen Baum, Bevan Bass	Hot Chips 23.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Daniel Sanchez, Christos Kozyrakis	Scalable and Efficient Fine-Grained Cache Partitioning with Vantage.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Wilson Wai Lun Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt	Kilo TM: Hardware Transactional Memory for GPU Architectures.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Doug Burger, Stephen W. Keckler, Mark Papermaster	Charles R. (Chuck) Moore (1961 - 2012).	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Shane Greenstein	The Range of Linus' Law.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Manish Arora, Siddhartha Nath, Subhra Mazumdar, Scott B. Baden, Dean M. Tullsen	Redefining the Role of the CPU in the Era of CPU-GPU Integration.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Saturnino Garcia, Donghwan Jeon, Christopher M. Louie, Michael Bedford Taylor	The Kremlin Oracle for Sequential Code Parallelization.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Thomas F. Wenisch, Alper Buyuktosunoglu	Energy-Aware Computing.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	David May	The XMOS Architecture and XS1 Chips.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Richard H. Stern	Standardization Skullduggery Never Ends: Apple v. Motorola.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Alexander Branover, Denis Foley, Maurice Steinman	AMD Fusion APU: Llano.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene	Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Simone Campanoni, Timothy M. Jones, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks	Helix: Making the Extraction of Thread-Level Parallelism Mainstream.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Ismael Gómez Miguelez, Vuk Marojevic, Antoni Gelonch Bosch	Resource Management for Software-Defined Radio Clouds.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Min Xie, Yutong Lu, Kefei Wang, Lu Liu, Hongjia Cao, Xuejun Yang	Tianhe-1A Interconnect and Message-Passing Services.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Qingyuan Deng, Luiz E. Ramos, Ricardo Bianchini, David Meisner, Thomas F. Wenisch	Active Low-Power Modes for Main Memory with MemScale.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Hengjie Li, Wenting He, Yang Chen, Lieven Eeckhout, Olivier Temam, Chengyong Wu	SWAP: Parallelization through Algorithm Substitution.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Hadi Esmaeilzadeh, Ting Cao, Xi Yang, Stephen Blackburn, Kathryn S. McKinley	What is Happening to Power, Performance, and Software?	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Feng Li, Antoniu Pop, Albert Cohen	Automatic Extraction of Coarse-Grained Data-Flow Threads from Imperative Programs.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Javier Verdú, Alex Pajuelo, Mateo Valero	The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Boris Grot, Damien Hardy, Pejman Lotfi-Kamran, Babak Falsafi, Chrysostomos Nicopoulos, Yiannakis Sazeides	Optimizing Data-Center TCO with Scale-Out Processors.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Shane Greenstein	The Secret Life of Wally Madhavani.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Fabrice Harrouet	Designing a Multicore and Multiprocessor Individual-Based Simulation Engine.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Hung-Wei Tseng, Dean M. Tullsen	Eliminating Redundant Computation and Exposing Parallelism through Data-Triggered Threads.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Rich Belgard	Yale N. Patt Receives the Inaugural IEEE B. Ramakrishna Rau Award.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Erik R. Altman	Top Picks, Columnists, and Artists.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg	FabScalar: Automating Superscalar Core Design.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Erik R. Altman	The Odd Couple: Hardware and Software.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Jason Mars, Lingjia Tang, Kevin Skadron, Mary Lou Soffa, Robert Hundt	Increasing Utilization in Modern Warehouse-Scale Computers Using Bubble-Up.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Md Kamruzzaman, Steven Swanson, Dean M. Tullsen	Underclocked Software Prefetching: More Cores, Less Energy.	IEEE Micro	2012	DBLP DOI BibTeX RDF
1	Ayse Kivilcim Coskun, David Atienza, Mohamed M. Sabry, Jie Meng	Attaining Single-Chip, High-Performance Computing through 3D Systems with Active Cooling.	IEEE Micro	2011	DBLP DOI BibTeX RDF	active cooling, 3D liquid-cooled systems, multiprocessor systems, emerging technologies, energy-aware systems, temperature-aware design
1	Richard Mateosian	Effective Communication [review of ".....Trees, Maps, and Theorems: Effective Commuincation for Rational Minds" (Doumont, J.-L.; 2009)].	IEEE Micro	2011	DBLP DOI BibTeX RDF	communication, documents, presentations
1	Craig M. Wittenbrink, Emmett Kilgariff, Arjun Prabhu	Fermi GF100 GPU Architecture.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Toshihiro Hanawa, Shin'ichi Miura, Taisuke Boku	Peach: A Multicore Communication System on Chip with PCI Express.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter	Thread Cluster Memory Scheduling.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	Energy-Aware Accounting and Billing in Large-Scale Computing Facilities.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José A. Tierno, Pradip Bose, Alper Buyuktosunoglu	Introducing the Adaptive Energy Management Features of the Power7 Chip.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks	Voltage Noise in Production Processors.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Wei Huang, Malcolm Allen-Ware, John B. Carter, Mircea R. Stan, Edmund Cheng	Temperature-Aware Architecture: Lessons and Opportunities.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Hiroshi Shimamoto, Takayuki Yamashita, Misao Kubota, Hirotaka Maruyama	Advanced Camera Technologies for Broadcasting.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Ravi Iyer, Sadagopan Srinivasan, Omesh Tickoo, Zhen Fang, Ramesh Illikkal, Steven Zhang, Vineet Chadha, Paul M. Stillwell, Seung Eun Lee	CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Shane Greenstein	The Direction of Broadband Spillovers.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt	Data Marshaling for Multicore Systems.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Erik R. Altman	Very Large-Scale Systems and Some History.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	David Brooks	CPUs, GPUs, and Hybrid Computing.	IEEE Micro	2011	DBLP DOI BibTeX RDF	GPU, high-performance computing, CPU, hybrid computing
1	Matthew A. Watkins, David H. Albonesi	ReMAP: A Reconfigurable Architecture for Chip Multiprocessors.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Vijayalakshmi Srinivasan	Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis
1	Jeffrey Brown, Sandra Woodward, Brian Bass, Charlie Johnson	IBM Power Edge of Network Processor: A Wire-Speed System on a Chip.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Craig Court, Paul Kelly	Loop-Directed Mothballing: Power Gating Execution Units Using Runtime Loop Analysis.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov	Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	systems on chips, physical synthesis
1	Richard H. Stern	Standardization Skullduggery Revisited.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Ron O. Dror, J. P. Grossman, Kenneth M. Mackenzie, Brian Towles, Edmond Chow, John K. Salmon, Cliff Young, Joseph A. Bank, Brannon Batson, David E. Shaw, Jeffrey Kuskin, Richard H. Larson, Mark A. Moraes	Overcoming Communication Latency Barriers in Massively Parallel Scientific Computation.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Yale N. Patt, Onur Mutlu	Top Picks [Guest editors' introduction].	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Stijn Polfliet, Frederick Ryckbosch, Lieven Eeckhout	Automated Full-System Power Characterization.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Natalie D. Enright Jerger, Mikko H. Lipasti	Systems for Very Large-Scale Computing.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Brian W. Curran, Lee Eisen, Eric M. Schwarz, Pak-kin Mak, James D. Warnock, Patrick J. Meaney, Michael F. Fee	The zEnterprise 196 System and Microprocessor.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Jeremy S. Meredith, Philip C. Roth, Kyle Spafford, Jeffrey S. Vetter	Performance Implications of Nonuniform Device Topologies in Scalable Heterogeneous Architectures.	IEEE Micro	2011	DBLP DOI BibTeX RDF	nonuniformity, heterogeneous GPUs, data-transfer performance, GPU
1	John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Cohesion: An Adaptive Hybrid Memory Model for Accelerators.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Jose Renau, Will Eatherton	Hot Chips 22.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco	GPUs and the Future of Parallel Computing.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Siegfried Benkner, Sabri Pllana, Jesper Larsson Träff, Philippas Tsigas, Uwe Dolinsky, Cédric Augonnet, Beverly Bachmayer, Christoph W. Kessler, David Moloney, Vitaly Osipov	PEPPHER: Efficient and Productive Usage of Hybrid Computing Systems.	IEEE Micro	2011	DBLP DOI BibTeX RDF	PEPPHER, GPU, multicore, CPU, hybrid computing
1	David Rohr, Matthias Bach, Matthias Kretz, Volker Lindenstruth	Multi-GPU DGEMM and High Performance Linpack on Highly Energy-Efficient Clusters.	IEEE Micro	2011	DBLP DOI BibTeX RDF	multi-GPU, HPL, High Performance Linpack, DGEMM, double-precision general matrix multiply, GPGPU, system architecture, Green IT, heterogeneous (hybrid) systems

Publications at "IEEE Micro"( http://dblp.L3S.de/Venues/IEEE_Micro )