| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Tung-Hua Yeh, Sying-Jyan Wang |
Power-Aware High-Level Synthesis With Clock Skew Management.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Chi Tsao, Ken Choi |
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahdi Shabany, P. Glenn Gulak |
A 675 Mbps, 4 $\times$ 4 64-QAM K-Best MIMO Detector in 0.13 $\mu{\rm m}$ CMOS. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Resolution of Diagnosis Based on Transition Faults. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung |
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungseob Lee, Nam Sung Kim |
Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kun-Hung Tsai, Shen-Iuan Liu |
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Phi-Hung Pham, Jongsun Park, Phuong Mau, Chulwoo Kim |
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongbin Sun, Chuanyin Liu, Wei Xu, Jizhong Zhao, Nanning Zheng, Tong Zhang |
Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Fu Liu, Pedro Reviriego, Juan Antonio Maestro |
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Faiz-ul Hassan, Wim Vanderbauwhede, Fernando Rodríguez Salazar |
Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi |
ORION 2.0: A Power-Area Simulator for Interconnection Networks. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun |
Reliability Modeling and Management of Nanophotonic On-Chip Networks. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ehsan Pakbaznia, Massoud Pedram |
Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Costagliola, D. de Caro, Antonio Girardi, Roberto Izzi, N. Rinaldi, M. Spirito, P. Spirito |
An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Duo Li, Eduardo H. Pacheco, Murli Tirumala, Lingli Wang |
General Parameterized Thermal Modeling for High-Performance Microprocessor Design. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar |
FISH: Fast Instruction SyntHesis for Custom Processors. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaydeep P. Kulkarni, Kaushik Roy |
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elio Consoli, Gaetano Palumbo, Melita Pennisi |
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu |
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sang Phill Park, Dongsoo Lee, Kaushik Roy |
Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez |
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ning Chen, Zhiyuan Yan, Maximilien Gadouleau, Ying Wang, Bruce W. Suter |
Rank Metric Decoder Architectures for Random Linear Network Coding With Error Control. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurice Meijer, José Pineda de Gyvez |
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic |
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, Jianhong Xiao, José Silva-Martínez |
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinwook Jang, Olivier Franza, Wayne Burleson |
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Younghoon Lee, Jungsoo Kim, Chong-Min Kyung |
Energy-Aware Video Encoding for Image Quality Improvement in Battery-Operated Surveillance Camera. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig Schlottmann, Csaba Petre, Paul E. Hasler |
A High-Level Simulink-Based Tool for FPAA Configuration. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel |
AdNoC: Runtime Adaptive Network-on-Chip Architecture. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti |
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To |
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiang Fu, Huawei Li, Xiaowei Li |
Testable Path Selection and Grouping for Faster Than At-Speed Testing. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Antonis M. Paschalis, Ioannis Voyiatzis, Dimitris Gizopoulos |
Accumulator Based 3-Weight Pattern Generation. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Geng-Ming Chiu, James Chien-Mo Li |
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vamshi Krishna Manthena, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo |
A Low-Power Single-Phase Clock Multiband Flexible Divider. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie |
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig Schlottmann, David N. Abramson, Paul E. Hasler |
A MITE-Based Translinear FPAA. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | B. Ramkumar, Harish M. Kittur |
Low-Power and Area-Efficient Carry Select Adder. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria |
Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum |
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Wen Chen, Ruo He Yao, Wei Jing Wu |
Efficient Modulo 2n+1 Multipliers. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Adam B. Kinsman, Nicola Nicolici |
A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aida Todri, Malgorzata Marek-Sadowska |
Power Delivery for Multicore Systems. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici |
Design-for-Debug Architecture for Distributed Embedded Logic Analysis. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | J. G. Mueller, Resve A. Saleh |
Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Performance Optimization Using Variable-Latency Design Style. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman |
Clock Distribution Networks in 3-D Integrated Systems. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yufu Zhang, Ankur Srivastava |
Accurate Temperature Estimation Using Noisy Thermal Sensors for Gaussian and Non-Gaussian Cases. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuebin Wu, Zhiyuan Yan |
Efficient CODEC Designs for Crosstalk Avoidance Codes Based on Numeral Systems. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Ying Tsai, Chung-Ho Chen |
Energy-Efficient Trace Reuse Cache for Embedded Processors. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoke Qin, Chetan Muthry, Prabhat Mishra |
Decoding-Aware Compression of FPGA Bitstreams. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Fixed-State Tests for Delay Faults in Scan Designs. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sourajeet Roy, Anestis Dounavis |
Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu |
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangmin Kim, Gerald E. Sobelman, Hanho Lee |
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hariharan Sankaran, Srinivas Katkoori |
Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | R. Gutierrez, J. Valls |
Low Cost Hardware Implementation of Logarithm Approximation. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Minki Cho, Jason Schlessman, Wayne Wolf, Saibal Mukhopadhyay |
Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan |
CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi |
High Performance and Area Efficient Flexible DSP Datapath Synthesis. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cathy Qun Xu, Chun Jason Xue, Edwin Hsing-Mean Sha |
Energy-Efficient Joint Scheduling and Application-Specific Interconnection Design. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt |
A Multi-Granularity Power Modeling Methodology for Embedded Processors. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat Seng Yeo |
Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsieh-Hung Hsieh, Huan-Sheng Chen, Ping-Hsi Hung, Liang-Hung Lu |
Experimental 5-GHz RF Frontends for Ultra-Low-Voltage and Ultra-Low-Power Operations. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | David C. W. Ng, David K. K. Kwong, Ngai Wong |
A Sub-1 V, 26 muW, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry |
A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Arindam Basu, Paul E. Hasler |
A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Chen, Jun Yang, Longxing Shi |
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Baradaran Tahoori |
High Resolution Application Specific Fault Diagnosis of FPGAs. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yasser Ismail, Mohsen Shaaban, Jason McNeely, Magdy A. Bayoumi |
An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari |
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | C.-W. Lin, M. C.-T. Chao, Y.-S. Huang |
A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | H.-C. Kuo, L.-C. Wu, H.-T. Huang, S.-T. Hsu, Y.-L. Lin |
A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao-I Yang, Wei Hwang, Ching-Te Chuang |
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chua-Chin Wang, Chia-Hao Hsu, Szu-Chia Liao, Yi-Cheng Liu |
A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy |
Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | N. K. Jha |
Editorial Announcing a New Editor-in-Chief. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Selçuk Köse, Emre Salman, Eby G. Friedman |
Shielding Methodologies in the Presence of Power/Ground Noise. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Broadside and Functional Broadside Tests for Partial-Scan Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim |
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehran Mozaffari Kermani, Arash Reyhani-Masoleh |
A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiun-Ping Wang, Shiann-Rong Kuang, Shish-Chang Liang |
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinmiao Zhang, Fang Cai |
Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitris Magos, Ioannis Voyiatzis, Steffen Tarnick |
An Accumulator - Based Test-Per-Clock Scheme. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi |
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert |
Design Optimizations for Tiled Partially Reconfigurable Systems. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anita Kumari, Sanjukta Bhanja |
Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajiv V. Joshi, Rouwaida Kanj, V. Ramadurai |
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi |
EGRA: A Coarse Grained Reconfigurable Architectural Template. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram Pudi, K. Sridharan |
Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto |
Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jongyoon Jung, Taewhan Kim |
Scheduling and Resource Binding Algorithm Considering Timing Variation. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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