| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Tung-Hua Yeh, Sying-Jyan Wang |
Power-Aware High-Level Synthesis With Clock Skew Management.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou |
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang |
WiT: Optimal Wiring Topology for Electromigration Avoidance. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Khurram, S. M. Rezaul Hasan |
A 3-5 GHz Current-Reuse gm-Boosted CG LNA for Ultrawideband in 130 nm CMOS. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhui Gu, Jianhui Wu, Danhong Gu, Meng Zhang, Longxing Shi |
All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Chi Tsao, Ken Choi |
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Chang Huang, Ke-Horng Chen, Wei-Yao Lin, Zon-Lon Lee, Kun-Wei Chang, Erica Hsu, Wenson Lee, Lin-Fwu Chen, Chris Lu |
Embedded I/O PAD Circuit Design for OTP Memory Power-Switch Functionality. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahdi Shabany, P. Glenn Gulak |
A 675 Mbps, 4 $\times$ 4 64-QAM K-Best MIMO Detector in 0.13 $\mu{\rm m}$ CMOS. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Resolution of Diagnosis Based on Transition Faults. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingoo Seok, Scott Hanson, David Blaauw, Dennis Sylvester |
Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{\rm dd}$ Operation. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu |
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung |
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hailong Jiao, Volkan Kursun |
Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungseob Lee, Nam Sung Kim |
Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Chih Hsieh, Wei Hwang |
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ta-Wen Kuan, Jhing-Fa Wang, Jia-Ching Wang, Po-Chuan Lin, Gaung-Hui Gu |
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sang-Hyun Cho, Chang-Kyo Lee, Sang-Gug Lee, Seung-Tak Ryu |
A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kun-Hung Tsai, Shen-Iuan Liu |
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinjin He, Huaping Liu, Zhongfeng Wang, Xinming Huang, Kai Zhang |
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Phi-Hung Pham, Jongsun Park, Phuong Mau, Chulwoo Kim |
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaehyouk Choi, Woonyun Kim, Kyutae Lim |
A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Taniya Siddiqua, Sudhanva Gurumurthi |
Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongbin Sun, Chuanyin Liu, Wei Xu, Jizhong Zhao, Nanning Zheng, Tong Zhang |
Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Atanu Chattopadhyay, Zeljko Zilic |
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | W. Paul Griffin, Anand Raghunathan, Kaushik Roy |
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Fu Liu, Pedro Reviriego, Juan Antonio Maestro |
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Faiz-ul Hassan, Wim Vanderbauwhede, Fernando Rodríguez Salazar |
Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi |
ORION 2.0: A Power-Area Simulator for Interconnection Networks. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun |
Reliability Modeling and Management of Nanophotonic On-Chip Networks. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ehsan Pakbaznia, Massoud Pedram |
Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | F. Garcia-Herrero, María José Canet, Javier Valls, Pramod K. Meher |
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Helge Anderson, Qiang Wang, Chirag Ravishankar |
Raising FPGA Logic Density Through Synthesis-Inspired Architecture. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Costagliola, D. de Caro, Antonio Girardi, Roberto Izzi, N. Rinaldi, M. Spirito, P. Spirito |
An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Hoyos, Cheongyuen W. Tsang, Johan Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic |
A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Manohar Ayinala, Michael Brown, Keshab K. Parhi |
Pipelined Parallel FFT Architectures via Folding Transformation. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Songjun Pan, Yu Hu, Xiaowei Li |
IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jose Luis Nunez-Yanez, Atukem Nabina, Eddie Hung, George Vafiadis |
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Duo Li, Eduardo H. Pacheco, Murli Tirumala, Lingli Wang |
General Parameterized Thermal Modeling for High-Performance Microprocessor Design. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Won-Young Lee, Lee-Sup Kim |
An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-$\mu$m CMOS. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sampo Tuuna, Ethiopia Nigussie, Jouni Isoaho, Hannu Tenhunen |
Modeling of Energy Dissipation in RLC Current-Mode Signaling. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar |
FISH: Fast Instruction SyntHesis for Custom Processors. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Moo-young Kim, Hokyu Lee, Chulwoo Kim |
PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Loop Acceleration Exploration for ASIP Architecture. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaroh Katoh, Kazuteru Namba, Hideo Ito |
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Amine Dehbaoui, Victor Lomné, Thomas Ordas, Lionel Torres, Michel Robert, Philippe Maurine |
Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuai Wang, Jie S. Hu, Sotirios G. Ziavras |
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jung-Won Han, Kwisung Yoo, Dongmyung Lee, Kangyeop Park, Wonseok Oh, Sung Min Park |
A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaydeep P. Kulkarni, Kaushik Roy |
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elio Consoli, Gaetano Palumbo, Melita Pennisi |
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu |
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sang Phill Park, Dongsoo Lee, Kaushik Roy |
Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez |
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Strauch |
Single Cycle Access Structure for Logic Test. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ning Chen, Zhiyuan Yan, Maximilien Gadouleau, Ying Wang, Bruce W. Suter |
Rank Metric Decoder Architectures for Random Linear Network Coding With Error Control. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai Liu, Evgeniy Belyaev, Jie Guo |
VLSI Architecture of Arithmetic Coder Used in SPIHT. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurice Meijer, José Pineda de Gyvez |
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic |
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, Jianhong Xiao, José Silva-Martínez |
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Anwar Hasan, Ashkan Hosseinzadeh Namin, Christophe Nègre |
Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fahad Ahmed, Linda Milor |
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinwook Jang, Olivier Franza, Wayne Burleson |
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Boyuan Yan, Sheldon X.-D. Tan, Lingfei Zhou, Jie Chen 0005, Ruijing Shen |
Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Saumya Chandra, Anand Raghunathan, Sujit Dey |
Variation-Aware Voltage Level Selection. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Younghoon Lee, Jungsoo Kim, Chong-Min Kyung |
Energy-Aware Video Encoding for Image Quality Improvement in Battery-Operated Surveillance Camera. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin |
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi |
Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhen Wang, Mark G. Karpovsky, Ajay Joshi |
Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig Schlottmann, Csaba Petre, Paul E. Hasler |
A High-Level Simulink-Based Tool for FPAA Configuration. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi |
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Francisco Barranco, Matteo Tomasi, Javier Díaz, Mauricio Vanegas, Eduardo Ros |
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheng Wei, Miodrag Potkonjak |
Scalable Hardware Trojan Diagnosis. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Ming Wong, M. L. Dennis Wong, Asoke K. Nandi, I. Hijazin |
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel |
AdNoC: Runtime Adaptive Network-on-Chip Architecture. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti |
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Zhao, Krishnendu Chakrabarty, Ryan Sturmer, Vamsee K. Pamula |
Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang |
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To |
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Duo Liu, Yi Wang, Zhiwei Qin, Zili Shao, Yong Guan |
A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiang Fu, Huawei Li, Xiaowei Li |
Testable Path Selection and Grouping for Faster Than At-Speed Testing. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Fei, Hao Yu, Wei Zhang, Kiat Seng Yeo |
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici |
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan |
The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Antonis M. Paschalis, Ioannis Voyiatzis, Dimitris Gizopoulos |
Accumulator Based 3-Weight Pattern Generation. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Weixun Wang, Prabhat Mishra |
System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jai-Ming Lin, Zhi-Xiong Hung |
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuan Guan, Yunsi Fei, Hai Lin |
Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Stelios Neophytou, Maria K. Michael |
Test Pattern Generation of Relaxed n-Detect Test Sets. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry |
On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB). |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Iris Hui-Ru Jiang, Hua-Yu Chang |
ECOS: Stable Matching Based Metal-Only ECO Synthesis. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Geng-Ming Chiu, James Chien-Mo Li |
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo |
A Low-Power Single-Phase Clock Multiband Flexible Divider. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato |
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuan-Ho Chen, Tsin-Yuan Chang |
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ang-Chih Hsieh, TingTing Hwang |
TSV Redundancy: Architecture and Design Issues in 3-D IC. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty |
Physical-Defect Modeling and Optimization for Fault-Insertion Test. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie |
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
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