| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Marcel Gort, Jason Helge Anderson |
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham |
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elena Kakoulli, Vassos Soteriou, Theocharis Theocharides |
Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Jen Wei, Howard Chen, Sao-Jie Chen |
Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-Grid Analysis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Giorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos |
Crossbar NoCs Are Scalable Beyond 100 Nodes. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, David Atienza |
Neural Network-Based Thermal Simulation of Integrated Circuits on GPUs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yinghong Zhou, Emad Gad, Michel S. Nakhla, Ramachandra Achar |
Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sourasis Das, Ansuman Banerjee, Pallab Dasgupta |
Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianchao Lu, Xiaomi Mao, Baris Taskin |
Integrated Clock Mesh Synthesis With Incremental Register Placement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Salamy, J. Ramanujam |
An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ibrahim N. Hajj |
Extended Nodal Analysis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mu-Shun Matt Lee, Wei-Ting Liao, Chien-Nan Jimmy Liu |
Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhuo Li, Ying Zhou, Weiping Shi |
$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong |
A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyungmin Cho, Larkhoon Leem, Subhasish Mitra |
ERSA: Error Resilient System Architecture for Probabilistic Applications. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Wei Lin, Po-Wei Lee, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng |
An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yung-Chih Chen, Chun-Yao Wang |
Logic Restructuring Using Node Addition and Removal. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Komail M. H. Badami, Shreepad Karmalkar |
Quasi-Static Compact Model for Coupling Between Aligned Contacts on Finite Substrates With Insulating or Conducting Backplanes. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingzhi Gao, Zuochang Ye, Yan Wang, Zhiping Yu |
Efficient Full-Chip Statistical Leakage Analysis Based on Fast Matrix Vector Product. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jongwon Lee, Duo Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Dan Jiao |
A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano |
OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles |
Low-Energy Standby-Sparing for Hard Real-Time Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato |
On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Zhao, Krishnendu Chakrabarty |
Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin Cui, Douglas L. Maskell |
A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal Aware Scheduling. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Rabenalt, Michael Richter, Frank Poehl, Michael Gössel |
Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun Seomun, Insup Shin, Youngsoo Shin |
Synthesis of Active-Mode Power-Gating Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian |
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Samson Melamed, Thorlindur Thorolfsson, T. Robert Harris, Shivam Priyadarshi, Paul D. Franzon, Michael B. Steer, W. Rhett Davis |
Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan |
A Technique for Test Coverage Closure Using GoldMine. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer |
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Maffezzoni |
Stochastic Analysis of Switched-Capacitor Circuits for Sampled Data Converters. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm |
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak |
ISPD11: Power-Driven Flip-Flop Merging and Relocation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Guoyong Shi, Grantham K. H. Pang, Ngai Wong |
Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dukyoung Yun, Sungchan Kim, Soonhoi Ha |
A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Afsaneh Nassery, Osman Emir Erol, Sule Ozev, Marian Verhelst |
Test Signal Development and Analysis for OFDM Systems RF Front-End Parameter Extraction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang |
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xue-Yang Zhu, Twan Basten, Marc Geilen, Sander Stuijk |
Efficient Retiming of Multirate DSP Algorithms. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sonali Chouhan, M. Balakrishnan, Ranjan Bose |
System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Hu, Cheng-Kok Koh |
Guest Editorial Special Section on the 2011 International Symposium on Physical Design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing Chiu Tam, R. D. (Shawn) Blanton |
SLIDER: Simulation of Layout-Injected Defects for Electrical Responses. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chengmo Yang, Alex Orailoglu |
Tackling Resource Variations Through Adaptive Multicore Execution Frameworks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Jin, Satoshi Goto |
Hilbert Transform-Based Workload Prediction and Dynamic Frequency Scaling for Power-Efficient Video Encoding. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunsun Park, Sungjoo Yoo, Sunggu Lee |
A Multistep Tag Comparison Method for a Low-Power L2 Cache. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Lu Wan, Deming Chen |
Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom J. Kazmierski, Leran Wang, Bashir M. Al-Hashimi, Geoff V. Merrett |
An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Diana Marculescu, Peng Li |
Guest Editorial Special Section on PAR-CAD: Parallel CAD Algorithms and CAD for Parallel Architectures/Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tan Yan, Martin D. F. Wong |
Correctly Model the Diagonal Capacity in Escape Routing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Joon-Sung Yang, Nur A. Touba |
Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaeyong Chung, Jacob A. Abraham |
Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Myung-Chul Kim, Dongjin Lee, Igor L. Markov |
SimPL: An Effective Placement Algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng |
Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyue-Kung Lu, Zhen-Yu Wang, Yi-Ming Tsai, Jiann-Liang Chen |
Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jorge Fernandez Villena, Luis Miguel Silveira |
Exploiting Parallelism for Improved Automation of Multidimensional Model Order Reduction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar |
Physically-Aware N-Detect Test. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao-Chiao Hong |
A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang |
Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongxia Fang, Krishnendu Chakrabarty, Zhiyuan Wang, Xinli Gu |
Reproduction and Detection of Board-Level Functional Failure. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong |
Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints". |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Melinda Y. Agyekum, Steven M. Nowick |
Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bing Shi, Yufu Zhang, Ankur Srivastava |
Accelerating Gate Sizing Using Graphics Processing Units. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Nachiket Kapre, André DeHon |
${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu, Gregory K. Chen |
A Reliable Routing Architecture and Algorithm for NoCs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongsoo Lee, Kaushik Roy |
Viterbi-Based Efficient Test Data Compression. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin S. Sapatnekar |
Editorial. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Khaled R. Heloue, Sari Onaissi, Farid N. Najm |
Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald |
Design-Aware Mask Inspection. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hana Chockler, Daniel Kroening, Mitra Purandare |
Computing Mutation Coverage in Interpolation-Based Model Checking. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Walid Ibrahim, Valeriu Beiu, Azam Beg |
GREDA: A Fast and More Accurate Gate Reliability EDA Tool. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yao-Lin Jiang, Hai-Bao Chen |
Application of General Orthogonal Polynomials to Fast Simulation of Nonlinear Descriptor Systems Through Piecewise-Linear Approximation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Haifeng Qian, Phillip J. Restle, Joseph N. Kozhaya, Clifford L. Gunion |
Subtractive Router for Tree-Driven-Grid Clocks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Johann Knechtel, Igor L. Markov, Jens Lienig |
Assembling 2-D Blocks Into 3-D Chips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
Memory-Efficient On-Chip Network With Adaptive Interfaces. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Welp, Nathan Kitchen, Andreas Kuehlmann |
Hardware Acceleration for Constraint Solving for Random Simulation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze |
Postgrid Clock Routing for High Performance Microprocessor Designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elif Alpaslan, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Jennifer Dworak |
NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongjin Lee, Igor L. Markov |
Obstacle-Aware Clock-Tree Shaping During Placement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Zhao, Krishnendu Chakrabarty |
Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra |
Carbon Nanotube Robust Digital VLSI. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ender Yilmaz, Sule Ozev |
Test Application for Analog/RF Circuits With Low Computational Burden. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas |
HORNET: A Cycle-Level Multicore Simulator. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic |
Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang |
$2^{n}$ Pattern Run-Length for Test Data Compression. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kun Yuan, Bei Yu, David Z. Pan |
E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu |
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Adam B. Kinsman, Nicola Nicolici |
Automated Range and Precision Bit-Width Allocation for Iterative Computations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Osnat Keren, Ilya Levin, Radomir S. Stankovic |
Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuanxing Xiong, Jia Wang |
Dual Algorithms for Vectorless Power Grid Verification Under Linear Current Constraints. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Hsiang Kao, Ming Yang, N. Sertac Artan, H. Jonathan Chao |
CNoC: High-Radix Clos Network-on-Chip. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenjie Gu |
QLMOR: A Projection-Based Nonlinear Model Order Reduction Approach Using Quadratic-Linear Representation of Nonlinear Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xueqian Zhao, Yonghe Guo, Xiaodao Chen, Zhuo Feng, Shiyan Hu |
Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Li, Michael S. Hsiao |
3-D Parallel Fault Simulation With GPGPU. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif |
Simultaneous Layout Migration and Decomposition for Double Patterning Technology. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Prashant Saxena, Yao-Wen Chang |
Guest Editorial. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Po-Hung Lin, Chih-Cheng Hsu, Yao-Tsung Chang |
Post-Placement Power Optimization With Multi-Bit Flip-Flops. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Yuan, Sean Leventhal, Junjun Gu, Gang Qu |
TALk: A Temperature-Aware Leakage Minimization Technique for Real-Time Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohamed M. Sabry, Ayse Kivilcim Coskun, David Atienza, Tajana Simunic Rosing, Thomas Brunschwiler |
Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
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