Search results for "ISCA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti	Achieving predictable performance through better memory controller placement in many-core CMPs.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, chip multiprocessors, routing algorithms, memory controllers
1	Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, Alok N. Choudhary	Firefly: illuminating future network-on-chip with nanophotonics.	ISCA	2009	DBLP DOI BibTeX RDF	nanophotonics, interconnection networks, topology, hierarchical network
1	Jie Yu, Satish Narayanasamy	A case for an interleaving constrained shared-memory multi-processor.	ISCA	2009	DBLP DOI BibTeX RDF	parallel programming, multiprocessors, software reliability, concurrency bugs
1	Jinho Suh, Michel Dubois	Dynamic MIPS rate stabilization in out-of-order processors.	ISCA	2009	DBLP DOI BibTeX RDF	ooo processors, real-time systems, embedded systems, stabilization, variability
1	Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu, Antonia Zhai, Nikhil Mungre, Ankit Tarkas	Dynamic performance tuning for speculative threads.	ISCA	2009	DBLP DOI BibTeX RDF	parallelism, dynamic optimization, multicore, thread-level speculation
1	Stephen W. Keckler, Luiz André Barroso (eds.)	36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA	ISCA	2009	DBLP BibTeX RDF
1	Cagdas Dirik, Bruce L. Jacob	The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization.	ISCA	2009	DBLP DOI BibTeX RDF	solid state disks, performance, flash memory, storage systems
1	Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
1	Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Parthasarathy Ranganathan, Steven K. Reinhardt, Thomas F. Wenisch	Disaggregated memory for expansion and sharing in blade servers.	ISCA	2009	DBLP DOI BibTeX RDF	disaggregated memory, memory blades, memory capacity expansion, power and cost efficiencies
1	Pedro Diaz, Marcelo Cintra	Stream chaining: exploiting multiple levels of correlation in data prefetching.	ISCA	2009	DBLP DOI BibTeX RDF	data prefetching
1	Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers	Scalable high performance main memory system using phase-change memory technology.	ISCA	2009	DBLP DOI BibTeX RDF	dram caching, phase change memory, wear leveling
1	Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger	Architecting phase change memory as a scalable dram alternative.	ISCA	2009	DBLP DOI BibTeX RDF	dram alternative, endurance, pcm, performance, scalability, power, energy, phase change memory
1	Yuejian Xie, Gabriel H. Loh	PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches.	ISCA	2009	DBLP DOI BibTeX RDF	cache, contention, sharing, multi-core, promotion, insertion
1	Vijay Nagarajan, Rajiv Gupta	ECMon: exposing cache events for monitoring.	ISCA	2009	DBLP DOI BibTeX RDF	cache events, recording for replay, speculation past barriers
1	Yefu Wang, Kai Ma, Xiaorui Wang	Temperature-constrained power control for chip multiprocessors with online model estimation.	ISCA	2009	DBLP DOI BibTeX RDF	power management, chip multiprocessor, feedback control
1	Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero	Hardware support for WCET analysis of hard real-time multicore systems.	ISCA	2009	DBLP DOI BibTeX RDF	wcet, interconnection network, multicore, hard real-time, real-time embedded systems, analyzability, cache partitioning
1	James Hamilton	Internet-scale service infrastructure efficiency.	ISCA	2009	DBLP DOI BibTeX RDF	internet-scale, efficiency
1	Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz	A fault tolerant, area efficient architecture for Shor's factoring algorithm.	ISCA	2009	DBLP DOI BibTeX RDF	cad, ion trap, control, quantum computing, layout
1	Ping Zhou, Bo Zhao, Jun Yang, Youtao Zhang	A durable and energy efficient main memory using phase change memory technology.	ISCA	2009	DBLP DOI BibTeX RDF	endurance, low power, phase change memory
1	Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi	Spatio-temporal memory streaming.	ISCA	2009	DBLP DOI BibTeX RDF	prefetching, spatial correlation, temporal correlation
1	Nan Jiang, John Kim, William J. Dally	Indirect adaptive routing on large scale interconnection networks.	ISCA	2009	DBLP DOI BibTeX RDF	dragonfly, routing, interconnection networks
1	Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González	Boosting single-thread performance in multi-core systems through fine-grain multi-threading.	ISCA	2009	DBLP DOI BibTeX RDF	core-fusion, single-thread performance, multicore, automatic parallelization, thread-level parallelism, speculative multithreading
1	Doe Hyun Yoon, Mattan Erez	Memory mapped ECC: low-cost error protection for last level caches.	ISCA	2009	DBLP DOI BibTeX RDF	last-level caches, reliability, error correction, soft error
1	Colin Blundell, Milo M. K. Martin, Thomas F. Wenisch	InvisiFence: performance-transparent memory ordering in conventional multiprocessors.	ISCA	2009	DBLP DOI BibTeX RDF	parallel programming, memory consistency
1	Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong	Multi-execution: multicore caching for data-similar executions.	ISCA	2009	DBLP DOI BibTeX RDF	data similar execution, multicore cache design, cmp
1	Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.	ISCA	2009	DBLP DOI BibTeX RDF	DRAM memories, bandwidth decoupling, decoupled DIMM
1	José A. Joao, Onur Mutlu, Yale N. Patt	Flexible reference-counting-based hardware acceleration for garbage collection.	ISCA	2009	DBLP DOI BibTeX RDF	garbage collection, reference counting
1	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, last-level cache, non-uniform cache access, nuca, private cache, r-nuca, reactive nuca, rotational interleaving, cache, replication, placement, chip multiprocessor, cmp, migration, multicore, cache coherence, multi-core, data replication, coherence, interleaving, data placement, data migration, cache management, shared cache, lookup
1	Thomas Moscibroda, Onur Mutlu	A case for bufferless routing in on-chip networks.	ISCA	2009	DBLP DOI BibTeX RDF	routing, multi-core, memory systems, on-chip networks
1	Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner	AnySP: anytime anywhere anyway signal processing.	ISCA	2009	DBLP DOI BibTeX RDF	fully programmable architecture, high-end signal processing, simd, single-instruction multiple-data parallelism, software defined radio, low-power architecture
1	Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay	Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism
1	Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin	Scaling the bandwidth wall: challenges in and avenues for CMP scaling.	ISCA	2009	DBLP DOI BibTeX RDF	analytical model, memory bandwidth, chip multi-processor
1	Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edward Suh, Marten van Dijk, Srinivas Devadas	Application-aware deadlock-free oblivious routing.	ISCA	2009	DBLP DOI BibTeX RDF	systems-on-chip, oblivious routing, on-chip interconnection networks
1	Abhishek Bhattacharjee, Margaret Martonosi	Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors.	ISCA	2009	DBLP DOI BibTeX RDF	intel tbb, thread criticality prediction, parallel processing, caches, dvfs
1	John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal C. Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	Rigel: an architecture and scalable programming interface for a 1000-core accelerator.	ISCA	2009	DBLP DOI BibTeX RDF	low-level programming interface, computer architecture, accelerator
1	Michael D. Powell, Arijit Biswas, Shantanu Gupta, Shubhendu S. Mukherjee	Architectural core salvaging in a multi-core processor for hard-error tolerance.	ISCA	2009	DBLP DOI BibTeX RDF	core salvaging, hard errors, reliability, redundancy
1	Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig	Performance and power of cache-based reconfigurable computing.	ISCA	2009	DBLP DOI BibTeX RDF	c-to-gates, c-to-hardware, co-processor accelerator, many-cache, synthesis compiler, fpga, caches
1	Sunpyo Hong, Hyesoon Kim	An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness.	ISCA	2009	DBLP DOI BibTeX RDF	GPU architecture, warp level parallelism, analytical model, cuda, performance estimation, memory level parallelism
1	Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi	Phastlane: a rapid transit optical routing network.	ISCA	2009	DBLP DOI BibTeX RDF	nanophotonics, interconnection networks, multicore, optical interconnects
1	Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Trevor N. Mudge	End-to-end performance forecasting: finding bottlenecks before they happen.	ISCA	2009	DBLP DOI BibTeX RDF	performance analysis, critical path analysis
1	Andrew D. Hilton, Amir Roth	Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint processors, load-store queues
1	Krishna K. Rangan, Gu-Yeon Wei, David Brooks	Thread motion: fine-grained power management for multi-core systems.	ISCA	2009	DBLP DOI BibTeX RDF	multi-core power management, thread motion, dvfs
1	Katherine A. Yelick	Ten ways to waste a parallel computer.	ISCA	2009	DBLP DOI BibTeX RDF	parallel computer, energy
1	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, stream programming, multi-core processors
1	Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González	End-to-end register data-flow continuous self-test.	ISCA	2009	DBLP DOI BibTeX RDF	control logic, end-to-end protection, online testing, design errors, degradation
1	Abdullah Muzahid, Darío Suárez Gracia, Shanxiang Qi, Josep Torrellas	SigRace: signature-based data race detection.	ISCA	2009	DBLP DOI BibTeX RDF	SigRace, concurrency defect, signature, timestamp, data race, happened-before
1	Nathan Clark, Amir Hormati, Scott A. Mahlke	VEAL: Virtualized Execution Accelerator for Loops.	ISCA	2008	DBLP DOI BibTeX RDF
1	Alex Shye, Berkin Özisikyilmaz, Arindam Mallik, Gokhan Memik, Peter A. Dinda, Robert P. Dick, Alok N. Choudhary	Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction.	ISCA	2008	DBLP DOI BibTeX RDF
1	Kevin T. Lim, Parthasarathy Ranganathan, Jichuan Chang, Chandrakant D. Patel, Trevor N. Mudge, Steven K. Reinhardt	Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments.	ISCA	2008	DBLP DOI BibTeX RDF
1	Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn	Corona: System Implications of Emerging Nanophotonic Technology.	ISCA	2008	DBLP DOI BibTeX RDF
1	Radu Teodorescu, Josep Torrellas	Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi	A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies.	ISCA	2008	DBLP DOI BibTeX RDF
1	Shimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael Ryan, Evangelos Vlachos	Flexible Hardware Acceleration for Instruction-Grain Program Monitoring.	ISCA	2008	DBLP DOI BibTeX RDF
1		35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China	ISCA	2008	DBLP BibTeX RDF
1	Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston	A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.	ISCA	2008	DBLP DOI BibTeX RDF
1	Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matthew I. Frank	Fetch-Criticality Reduction through Control Independence.	ISCA	2008	DBLP DOI BibTeX RDF
1	John Kim, William J. Dally, Steve Scott, Dennis Abts	Technology-Driven, Highly-Scalable Dragonfly Topology.	ISCA	2008	DBLP DOI BibTeX RDF
1	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri	iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures.	ISCA	2008	DBLP DOI BibTeX RDF
1	Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, David A. Wood	TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory.	ISCA	2008	DBLP DOI BibTeX RDF
1	Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti	Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support.	ISCA	2008	DBLP DOI BibTeX RDF
1	Lucas Kreger-Stickles, Mark Oskin	Microcoded Architectures for Ion-Tap Quantum Computers.	ISCA	2008	DBLP DOI BibTeX RDF
1	Onur Mutlu, Thomas Moscibroda	Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems.	ISCA	2008	DBLP DOI BibTeX RDF
1	Xiaoyao Liang, Gu-Yeon Wei, David Brooks	ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.	ISCA	2008	DBLP DOI BibTeX RDF
1	Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu	Trading off Cache Capacity for Reliability to Enable Low Voltage Operation.	ISCA	2008	DBLP DOI BibTeX RDF
1	Pablo Montesinos, Luis Ceze, Josep Torrellas	DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently.	ISCA	2008	DBLP DOI BibTeX RDF
1	Taeho Kgil, David Roberts, Trevor N. Mudge	Improving NAND Flash Based Disk Caches.	ISCA	2008	DBLP DOI BibTeX RDF
1	Lee Baugh, Naveen Neelakantam, Craig B. Zilles	Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory.	ISCA	2008	DBLP DOI BibTeX RDF
1	Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero	Software-Controlled Priority Characterization of POWER5 Processor.	ISCA	2008	DBLP DOI BibTeX RDF
1	Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott	Flexible Decoupled Transactional Memory Support.	ISCA	2008	DBLP DOI BibTeX RDF
1	Jae W. Lee, Man Cheuk Ng, Krste Asanovic	Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks.	ISCA	2008	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	3D-Stacked Memory Architectures for Multi-core Processors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz	Running a Quantum Circuit at the Speed of Data.	ISCA	2008	DBLP DOI BibTeX RDF
1	Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan	Intra-disk Parallelism: An Idea Whose Time Has Come.	ISCA	2008	DBLP DOI BibTeX RDF
1	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Online Estimation of Architectural Vulnerability Factor for Soft Errors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruden González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero	A Two-Level Load/Store Queue Based on Execution Locality.	ISCA	2008	DBLP DOI BibTeX RDF
1	Brandon Lucia, Joseph Devietti, Karin Strauss, Luis Ceze	Atom-Aid: Detecting and Surviving Atomicity Violations.	ISCA	2008	DBLP DOI BibTeX RDF
1	Franziska Roesner, Doug Burger, Stephen W. Keckler	Counting Dependence Predictors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Derek Hower, Mark D. Hill	Rerun: Exploiting Episodes for Lightweight Memory Race Recording.	ISCA	2008	DBLP DOI BibTeX RDF
1	Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das	MIRA: A Multi-layered On-Chip Interconnect Router Architecture.	ISCA	2008	DBLP DOI BibTeX RDF
1	Francis Tseng, Yale N. Patt	Achieving Out-of-Order Performance with Almost In-Order Complexity.	ISCA	2008	DBLP DOI BibTeX RDF
1	Haibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-Chung Yew, Frederic T. Chong	From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware.	ISCA	2008	DBLP DOI BibTeX RDF
1	Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana	Self-Optimizing Memory Controllers: A Reinforcement Learning Approach.	ISCA	2008	DBLP DOI BibTeX RDF
1	Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd M. Austin	Polymorphic On-Chip Networks.	ISCA	2008	DBLP DOI BibTeX RDF
1	Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Yen-Kuang Chen, Jatin Chhugani, Christopher J. Hughes, Changkyu Kim, Victor W. Lee, Anthony D. Nguyen	Atomic Vector Operations on Chip Multiprocessors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Brad Calder (eds.)	34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA	ISCA	2007	DBLP BibTeX RDF
1	Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen	Carbon: architectural support for fine-grained parallelism on chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	loop and task parallelism, CMP, architectural support
1	Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha	Express virtual channels: towards the ideal interconnection fabric.	ISCA	2007	DBLP DOI BibTeX RDF	packet-switching, flow-control, router design
1	Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler	Late-binding: enabling unordered load-store queues.	ISCA	2007	DBLP DOI BibTeX RDF	network flow control, memory disambiguation, late binding
1	Hany E. Ramadan, Christopher J. Rossbach, Donald E. Porter, Owen S. Hofmann, Bhandari Aditya, Emmett Witchel	MetaTM//TxLinux: transactional memory for an operating system.	ISCA	2007	DBLP DOI BibTeX RDF	MetaTM, OS support, TxLinux, transactional memory
1	Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang	A 64-bit stream processor architecture for scientific applications.	ISCA	2007	DBLP DOI BibTeX RDF	architecture, compiler, program language, high performance computing, scientific application, stream processor
1	Naveen Muralimanohar, Rajeev Balasubramonian	Interconnect design considerations for large NUCA caches.	ISCA	2007	DBLP DOI BibTeX RDF	non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models
1	Kyle J. Nesbit, James Laudon, James E. Smith	Virtual private caches.	ISCA	2007	DBLP DOI BibTeX RDF	quality of service, chip multiprocessor, soft real-time, shared caches, performance isolation
1	Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos	Mechanisms for store-wait-free multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	store buffer design, memory consistency models
1	Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott	An integrated hardware-software approach to flexible transactional memory.	ISCA	2007	DBLP DOI BibTeX RDF	RSTM, multiprocessors, transactional memory, cache coherence
1	Weirong Zhu, Vugranam C. Sreedhar, Ziang Hu, Guang R. Gao	Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures.	ISCA	2007	DBLP DOI BibTeX RDF	SSB, fine-grain synchronization, many-core
1	Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles	Hardware atomicity for reliable software speculation.	ISCA	2007	DBLP DOI BibTeX RDF	Java, optimization, checkpoint, atomicity, speculation, isolation
1	Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer	Adaptive insertion policies for high performance caching.	ISCA	2007	DBLP DOI BibTeX RDF	set dueling, set sampling, thrashing, replacement
1	Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam	Mechanisms for bounding vulnerabilities of processor structures.	ISCA	2007	DBLP DOI BibTeX RDF	redundant threading, microarchitecture, transient faults
1	Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas	ReCycle: : pipeline adaptation to tolerate process variation.	ISCA	2007	DBLP DOI BibTeX RDF	pipeline, process variation, clock skew
1	Kristen R. Walcott, Greg Humphreys, Sudhanva Gurumurthi	Dynamic prediction of architectural vulnerability from microarchitectural state.	ISCA	2007	DBLP DOI BibTeX RDF	architecture vulnerability factor, redundant multithreading, performance, reliability, microarchitecture

Publications at "ISCA"( http://dblp.L3S.de/Venues/ISCA )