Search results for "ISCA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, Stavros Volos, Yusuf Onur Koçberber, Javier Picorel, Almutaz Adileh, Djordje Jevdjic, Sachin Idgunji, Emre Özer, Babak Falsafi	Scale-out processors.	ISCA	2012	DBLP DOI BibTeX RDF
1	Minsoo Rhu, Mattan Erez	CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures.	ISCA	2012	DBLP DOI BibTeX RDF
1		39th International Symposium on Computer Architecture (ISCA 2012), June 9-13, 2012, Portland, OR, USA	ISCA	2012	DBLP BibTeX RDF
1	Jeongseob Ahn, Seongwook Jin, Jaehyuk Huh	Revisiting hardware-assisted page walks for virtualized systems.	ISCA	2012	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan	BOOM: Enabling mobile memory based low-power server DIMMs.	ISCA	2012	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, Michele Franceschini, Ashish Jagmohan, Luis Lastras	PreSET: Improving performance of phase change memories by exploiting asymmetry in write times.	ISCA	2012	DBLP DOI BibTeX RDF
1	Vasileios Kontorinis, Liuyi Eric Zhang, Baris Aksanli, Jack Sampson, Houman Homayoun, Eddie Pettis, Dean M. Tullsen, Tajana Simunic Rosing	Managing distributed UPS energy for effective power capping in data centers.	ISCA	2012	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Min Kyu Jeong, Michael Sullivan, Mattan Erez	The dynamic granularity memory system.	ISCA	2012	DBLP DOI BibTeX RDF
1	Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu	VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu	RAIDR: Retention-aware intelligent DRAM refresh.	ISCA	2012	DBLP DOI BibTeX RDF
1	Krishna T. Malladi, Frank A. Nothaft, Karthika Periyathambi, Benjamin C. Lee, Christos Kozyrakis, Mark Horowitz	Towards energy-proportional datacenter memory with mobile DRAM.	ISCA	2012	DBLP DOI BibTeX RDF
1	Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy Kurian John	A first-order mechanistic model for architectural vulnerability factor.	ISCA	2012	DBLP DOI BibTeX RDF
1	Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu	A case for exploiting subarray-level parallelism (SALP) in DRAM.	ISCA	2012	DBLP DOI BibTeX RDF
1	Olivier Temam	A defect-tolerant accelerator for emerging high-performance applications.	ISCA	2012	DBLP DOI BibTeX RDF
1	Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu	Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems.	ISCA	2012	DBLP DOI BibTeX RDF
1	Arkaprava Basu, Mark D. Hill, Michael M. Swift	Reducing memory reference energy with opportunistic virtual caching.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychronis Xekalakis	Boosting mobile GPU performance with a decoupled access/execute fragment processor.	ISCA	2012	DBLP DOI BibTeX RDF
1	Ioannis Doudalis, Milos Prvulovic	Euripus: A flexible unified hardware memory checkpointing accelerator for bidirectional-debugging and reliability.	ISCA	2012	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jason Mars, Naveen Kumar	BlockChop: Dynamic squash elimination for hybrid processor architecture.	ISCA	2012	DBLP DOI BibTeX RDF
1	Chao Li, Amer Qouneh, Tao Li	iSwitch: Coordinating and optimizing renewable energy powered server clusters.	ISCA	2012	DBLP DOI BibTeX RDF
1	Myoungsoo Jung, Ellis Herbert Wilson, Mahmut T. Kandemir	Physically Addressed Queueing (PAQ): Improving parallelism in Solid State Disks.	ISCA	2012	DBLP DOI BibTeX RDF
1	Joseph Devietti, Benjamin P. Wood, Karin Strauss, Luis Ceze, Dan Grossman, Shaz Qadeer	RADISH: Always-on sound and complete race detection in software and hardware.	ISCA	2012	DBLP DOI BibTeX RDF
1	R. Manikantan, Kaushik Rajan, R. Govindarajan	Probabilistic Shared Cache Management (PriSM).	ISCA	2012	DBLP DOI BibTeX RDF
1	Pranay Koka, Michael O. McCracken, Herb Schwetman, Chia-Hsin Owen Chen, Xuezhe Zheng, Ron Ho, Kannan Raj, Ashok V. Krishnamoorthy	A micro-architectural analysis of switched photonic multi-chip interconnects.	ISCA	2012	DBLP DOI BibTeX RDF
1	Yi Xu, Jun Yang 0002, Rami G. Melhem	Tolerating process variations in nanophotonic on-chip networks.	ISCA	2012	DBLP DOI BibTeX RDF
1	Melanie Kambadur, Kui Tang, Martha A. Kim	Harmony: Collection and analysis of parallel block vectors.	ISCA	2012	DBLP DOI BibTeX RDF
1	Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer	Scheduling heterogeneous multi-cores through performance impact estimation (PIE).	ISCA	2012	DBLP DOI BibTeX RDF
1	Nicolas Brunie, Sylvain Collange, Gregory Frederick Diamos	Simultaneous branch and warp interweaving for sustained GPU performance.	ISCA	2012	DBLP DOI BibTeX RDF
1	Aaron Carpenter, Jianyun Hu, Övünç Kocabas, Michael C. Huang, Hui Wu	Enhancing effective throughput for transmission line-based bus.	ISCA	2012	DBLP DOI BibTeX RDF
1	Mehmet Kayaalp, Meltem Ozsoy, Nael B. Abu-Ghazaleh, Dmitry Ponomarev	Branch regulation: Low-overhead protection from code reuse attacks.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jaikrishnan Menon, Marc de Kruijf, Karthikeyan Sankaralingam	iGPU: Exception support and speculative execution on GPUs.	ISCA	2012	DBLP DOI BibTeX RDF
1	Mahdi Nazm Bojnordi, Engin Ipek	PARDIS: A programmable memory controller for the DDRx interfacing standards.	ISCA	2012	DBLP DOI BibTeX RDF
1	Andrea Pellegrini, Joseph L. Greathouse, Valeria Bertacco	Viper: Virtual pipelines for enhanced reliability.	ISCA	2012	DBLP DOI BibTeX RDF
1	Evgeni Krimer, Patrick Chiang, Mattan Erez	Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures.	ISCA	2012	DBLP DOI BibTeX RDF
1	Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez	Improving writeback efficiency with decoupled last-write prediction.	ISCA	2012	DBLP DOI BibTeX RDF
1	David Wentzlaff, Christopher J. Jackson, Patrick Griffin, Anant Agarwal	Configurable fine-grain protection for multicore processor virtualization.	ISCA	2012	DBLP DOI BibTeX RDF
1	Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd D. Millstein, Madanlal Musuvathi	End-to-end sequential consistency.	ISCA	2012	DBLP DOI BibTeX RDF
1	Robert Martin, John Demme, Simha Sethumadhavan	TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks.	ISCA	2012	DBLP DOI BibTeX RDF
1	Gaurang Upasani, Xavier Vera, Antonio González	Setting an error detection infrastructure with low cost acoustic wave detectors.	ISCA	2012	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova	A case for random shortcut topologies for HPC interconnects.	ISCA	2012	DBLP DOI BibTeX RDF
1	Ting Cao, Stephen M. Blackburn, Tiejun Gao, Kathryn S. McKinley	The Yin and Yang of power and performance for asymmetric hardware and managed software.	ISCA	2012	DBLP DOI BibTeX RDF
1	Santosh Nagarakatte, Milo M. K. Martin, Steve Zdancewic	Watchdog: Hardware for safe and secure manual memory management and full memory safety.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim	FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion.	ISCA	2012	DBLP DOI BibTeX RDF
1	Nadathur Satish, Changkyu Kim, Jatin Chhugani, Hideki Saito, Rakesh Krishnaiyer, Mikhail Smelyanskiy, Milind Girkar, Pradeep Dubey	Can traditional programming bridge the Ninja performance gap for parallel computing applications?	ISCA	2012	DBLP DOI BibTeX RDF
1	Elliott Cooper-Balis, Paul Rosenfeld, Bruce Jacob	Buffer-on-board memory systems.	ISCA	2012	DBLP DOI BibTeX RDF
1	John Demme, Robert Martin, Adam Waksman, Simha Sethumadhavan	Side-channel vulnerability factor: A metric for measuring information leakage.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jonathan Valamehr, Melissa Chase, Seny Kamara, Andrew Putnam, Dan Shumow, Vinod Vaikuntanathan, Timothy Sherwood	Inspection resistant memory: Architectural support for security from physical examination.	ISCA	2012	DBLP DOI BibTeX RDF
1	Siddhartha Chhabra, Yan Solihin	i-NVMM: a secure non-volatile main memory system with incremental encryption.	ISCA	2011	DBLP DOI BibTeX RDF
1	Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Venkatraman Govindaraju, Marc de Kruijf, Karthikeyan Sankaralingam	Sampling + DMR: practical and low-overhead permanent fault detection.	ISCA	2011	DBLP DOI BibTeX RDF
1	Wing-Kei S. Yu, Ruirui C. Huang, Sarah Q. Xu, Sung-En Wang, Edwin Kan, G. Edward Suh	SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading.	ISCA	2011	DBLP DOI BibTeX RDF
1	David Meisner, Christopher M. Sadler, Luiz André Barroso, Wolf-Dietrich Weber, Thomas F. Wenisch	Power management of online data-intensive services.	ISCA	2011	DBLP DOI BibTeX RDF
1	Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu	Energy-efficient cache design using variable-strength error-correcting codes.	ISCA	2011	DBLP DOI BibTeX RDF
1	Joseph L. Greathouse, Zhiqiang Ma, Matthew I. Frank, Ramesh Peri, Todd M. Austin	Demand-driven software race detection using hardware performance counters.	ISCA	2011	DBLP DOI BibTeX RDF
1	Aaron Carpenter, Jianyun Hu, Jie Xu, Michael C. Huang, Hui Wu	A case for globally shared-medium on-chip interconnect.	ISCA	2011	DBLP DOI BibTeX RDF
1	Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li 0001	An abacus turn model for time/space-efficient reconfigurable routing.	ISCA	2011	DBLP DOI BibTeX RDF
1	Neal Clayton Crago, Sanjay J. Patel	OUTRIDER: efficient memory latency tolerance with decoupled strands.	ISCA	2011	DBLP DOI BibTeX RDF
1	Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen	Moguls: a model to explore the memory hierarchy for bandwidth improvements.	ISCA	2011	DBLP DOI BibTeX RDF
1	Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn	The role of optics in future high radix switch design.	ISCA	2011	DBLP DOI BibTeX RDF
1	Mehrtash Manoochehri, Murali Annavaram, Michel Dubois	CPPC: correctable parity protected cache.	ISCA	2011	DBLP DOI BibTeX RDF
1	Kai Ma, Xue Li, Ming Chen, Xiaorui Wang	Scalable power control for many-core architectures running multi-threaded applications.	ISCA	2011	DBLP DOI BibTeX RDF
1	Hadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, Doug Burger	Dark silicon and the end of multicore scaling.	ISCA	2011	DBLP DOI BibTeX RDF
1	Blas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato	Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks.	ISCA	2011	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Min Kyu Jeong, Mattan Erez	Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput.	ISCA	2011	DBLP DOI BibTeX RDF
1	Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan Valamehr, Timothy E. Levin, Ben Hardekopf, Ryan Kastner, Frederic T. Chong, Timothy Sherwood	Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security.	ISCA	2011	DBLP DOI BibTeX RDF
1	Thomas W. Barr, Alan L. Cox, Scott Rixner	SpecTLB: a mechanism for speculative address translation.	ISCA	2011	DBLP DOI BibTeX RDF
1	Ravi Iyer, Qing Yang, Antonio González (eds.)	38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA	ISCA	2011	DBLP BibTeX RDF
1	Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	A case for heterogeneous on-chip interconnects for CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu	Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees.	ISCA	2011	DBLP DOI BibTeX RDF
1	Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramoney	Bypass and insertion algorithms for exclusive last-level caches.	ISCA	2011	DBLP DOI BibTeX RDF
1	Atif Hashmi, Hugues Berry, Olivier Temam, Mikko H. Lipasti	Automatic abstraction and fault tolerance in cortical microachitectures.	ISCA	2011	DBLP DOI BibTeX RDF
1	Daniel Sanchez, Christos Kozyrakis	Vantage: scalable and efficient fine-grain cache partitioning.	ISCA	2011	DBLP DOI BibTeX RDF
1	Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic	Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators.	ISCA	2011	DBLP DOI BibTeX RDF
1	Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron	Energy-efficient mechanisms for managing thread context in throughput processors.	ISCA	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Rishi Agarwal, Pranav Garg 0001, Josep Torrellas	Rebound: scalable checkpointing for coherent shared memory.	ISCA	2011	DBLP DOI BibTeX RDF
1	Sriram Govindan, Anand Sivasubramaniam, Bhuvan Urgaonkar	Benefits and limitations of tapping into stored energy for datacenters.	ISCA	2011	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.	ISCA	2011	DBLP DOI BibTeX RDF
1	Sheng Ma, Natalie D. Enright Jerger, Zhiying Wang	DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip.	ISCA	2011	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt	Prefetch-aware shared resource management for multi-core systems.	ISCA	2011	DBLP DOI BibTeX RDF
1	Susmit Biswas, Mohit Tiwari, Timothy Sherwood, Luke Theogarajan, Frederic T. Chong	Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management.	ISCA	2011	DBLP DOI BibTeX RDF
1	Lingjia Tang, Jason Mars, Neil Vachharajani, Robert Hundt, Mary Lou Soffa	The impact of memory subsystem resource sharing on datacenter applications.	ISCA	2011	DBLP DOI BibTeX RDF
1	Jungju Oh, Milos Prvulovic, Alenka G. Zajic	TLSync: support for multiple fast barriers using on-chip transmission lines.	ISCA	2011	DBLP DOI BibTeX RDF
1	Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg	FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template.	ISCA	2011	DBLP DOI BibTeX RDF
1	Rishi Agarwal, Josep Torrellas	FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes.	ISCA	2011	DBLP DOI BibTeX RDF
1	Youngjin Kwon, Changdae Kim, Seungryoul Maeng, Jaehyuk Huh	Virtualizing performance asymmetric multi-core systems.	ISCA	2011	DBLP DOI BibTeX RDF
1	John Demme, Simha Sethumadhavan	Rapid identification of architectural bottlenecks via precise event counting.	ISCA	2011	DBLP DOI BibTeX RDF
1	Erika Gunadi, Mikko H. Lipasti	CRIB: consolidated rename, issue, and bypass.	ISCA	2011	DBLP DOI BibTeX RDF
1	Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau	Releasing efficient beta cores to market early.	ISCA	2011	DBLP DOI BibTeX RDF
1	Enric Herrero, José González, Ramon Canal	Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.	ISCA	2010	DBLP DOI BibTeX RDF	elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
1	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of inefficiency in general-purpose chips.	ISCA	2010	DBLP DOI BibTeX RDF	tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
1	Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger	Use ECP, not ECC, for hard failures in resistive memories.	ISCA	2010	DBLP DOI BibTeX RDF	hard failures, resistive memories, memory, error correction, phase change memory
1	Yunji Chen, Weiwu Hu, Tianshi Chen, Ruiyang Wu	LReplay: a pending period based deterministic replay scheme.	ISCA	2010	DBLP DOI BibTeX RDF	global clock, pending period, physical time order, multi-core processor, deterministic replay, dfd
1	Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi	A dynamically configurable coprocessor for convolutional neural networks.	ISCA	2010	DBLP DOI BibTeX RDF	dynamic reconfiguration, parallel computer architecture, convolutional neural networks
1	Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño, John P. Karidis	Morphable memory system: a robust architecture for exploiting multi-level phase change memories.	ISCA	2010	DBLP DOI BibTeX RDF	morphable memory, multi-level cell, phase change memory
1	John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Cohesion: a hybrid memory model for accelerators.	ISCA	2010	DBLP DOI BibTeX RDF	computer architecture, cache coherence, accelerator
1	Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John	The virtual write queue: coordinating DRAM and last-level cache policies.	ISCA	2010	DBLP DOI BibTeX RDF	cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
1	Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy	Silicon-photonic network architectures for scalable, power-efficient multi-chip systems.	ISCA	2010	DBLP DOI BibTeX RDF	interconnection networks, nanophotonics
1	Janghaeng Lee, Haicheng Wu, Madhumitha Ravichandran, Nathan Clark	Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications.	ISCA	2010	DBLP DOI BibTeX RDF	managed parallelism, threading, dynamic compilation
1	André Seznec, Uri C. Weiser, Ronny Ronen (eds.)	37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France	ISCA	2010	DBLP BibTeX RDF

Publications at "ISCA"( http://dblp.L3S.de/Venues/ISCA )