| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Naushad Alam, Bulusu Anand, Sudeb Dasgupta |
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance.  |
ISQED  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu |
Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni (eds.) |
Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012 |
ISQED |
2012 |
DBLP BibTeX RDF |
|
| 1 | Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura |
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada |
A design-for-test apparatus for measuring on-chip temperature with fine granularity. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De Micheli |
The combined effect of process variations and power supply noise on clock skew and jitter. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassan Hassan, Nizar Abdallah |
A complete power estimation methodology for DSP blocks in FPGAs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Zjajo, Nick van der Meijs, Rene van Leuken |
Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Albert H. Chang, Kewei Zuo, Jean Wang, Douglas Yu, Duane S. Boning |
Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis |
Functional composition: A new paradigm for performing logic synthesis. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Huang, Tianwei Zhang, Runsheng Wang, Changze Liu, Yuchao Liu, Ru Huang |
Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Eduardo Antunes, Matheus Soares, Alexandra Aguiar, Sergio Johann Filho, Marcos Sartori, Fabiano Hessel, César A. M. Marcon |
Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoC. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos |
Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Nishant Dhumane, Sandip Kundu |
Critical area driven dummy fill insertion to improve manufacturing yield. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai |
DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongtae Kim, Peng Li |
An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans |
Impact of C-elements in asynchronous circuits. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai |
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Abdel-Majeed, Mike Chen, Murali Annavaram |
A case for 3D stacked analog circuits in high-speed sensing systems. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaloo Rakheja, Vachan Kumar |
Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fahad Ahmed, Mohamed M. Sabry, David Atienza, Linda Milor |
Wearout-aware compiler-directed register assignment for embedded systems. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Takashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi |
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Richard Crisp, Bill Gervasi, Wael Zohni, Bel Haba |
Cost-minimized double die DRAM packaging for ultra-high performance DDR3 and DDR4 multi-rank server DIMMs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee |
Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Leslie Hwang, Kevin L. Lin, Martin D. F. Wong |
Thermal via structural design in three-dimensional integrated circuits. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rami F. Salem, Mohamed Al-Imam, Abdelrahman ElMously, Haitham Eissa, Ahmed Arafa, Mohab H. Anis |
High performance electrical driven hotspot detection solution for full chip design using a novel device parameter matching technique. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaiyuan Yang, Dae Hyun Kim, Sung Kyu Lim |
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu |
On lithography aware metal-fill insertion. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonathan Watkins, Jai Pollayil, Calvin Chow, Aveek Sarkar |
Chip-package power delivery network resonance analysis and co-design using time and frequency domain analysis techniques. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Mehryar Rahmatian, Vasileios Kontorinis, Shahin Golshan, Dean M. Tullsen |
Hot peripheral thermal management to mitigate cache temperature variation. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Felipe G. Magalhaes, Oliver B. Longhi, Sergio Johann Filho, Alexandra Aguiar, Fabiano Hessel |
NoC-based platform for embedded software design: An extension of the Hellfire Framework. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Keisuke Inoue, Mineo Kaneko |
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee, Duane C. Howard, John D. Cressler |
A self-testable SiGe LNA and Built-in-Self-Test methodology for multiple performance specifications of RF amplifiers. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas |
Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zafar Takhirov, Bobak Nazer, Ajay Joshi |
Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang |
Physical-design-friendly hierarchical logic built-in self-test - A case study. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bin Wu |
Dynamic range estimation for systems with control-flow structures. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake |
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahboobeh Ghorbani |
A variation and energy aware ILP formulation for task scheduling in MPSoC. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Riadul Islam |
A highly reliable SEU hardened latch and high performance SEU hardened flip-flop. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong Xu, Peng Li |
Design and optimization of power gating for DVFS applications. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenyun Pan, Azad Naeemi |
Device- and system-level performance modeling for graphene P-N junction logic. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Supriyo Maji, Pradip Mandal |
Effcient approaches to overcome non-convexity issues in analog design automation. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hironori Sakamoto, Shigetaka Kumashiro, Shigeo Sato, Naoki Wakita, Tohru Mogami |
HiSIM-RP: A reverse-profiling based 1st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Shen, Jun Lu, Qinru Qiu |
Learning based DVFS for simultaneous temperature, performance and energy management. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian |
Theory of redundancy for logic circuits to maximize yield/area. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Yu, Wen-Yao Chang, Kewei Zuo, Jean Wang, Douglas Yu, Duane S. Boning |
Methodology for analysis of TSV stress induced transistor variation and circuit performance. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsun Li, Meng-Hsueh Chiang |
Design issues and insights of multi-fin bulk silicon FinFETs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ho-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi |
A 3D IC designs partitioning algorithm with power consideration. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose |
A preliminary study on system-level impact of persistent main memory. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty |
Low complexity cross parity codes for multiple and random bit error correction. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
Bit error rate estimation in SRAM considering temperature fluctuation. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Le Maitre, Melanie Brocard, Alexis Farcy, Jean-Claude Marin |
Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mustafa Berke Yelten, Paul D. Franzon, Michael B. Steer |
Process mismatch analysis based on reduced-order models. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik |
Automated correction of design errors by edge redirection on High-Level Decision Diagrams. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Atsuki Inoue |
Comparison between power gating and DVFS from the viewpoint of energy efficiency. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jen-Yi Wuu, Mark Simmons, Malgorzata Marek-Sadowska |
Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Satyajit Desai, Sanghamitra Roy, Koushik Chakraborty |
Process variation aware DRAM design using block based adaptive body biasing algorithm. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rouwaida Kanj, Rajiv V. Joshi |
A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly |
Vertical Slit Field Effect Transistor in ultra-low power applications. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Davit Mirzoyan, Benny Akesson, Kees Goossens |
Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee |
Hierarchical power network synthesis for multiple power domain designs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Huang Kun, Yang Xu, Guoxing Zhao, Zuying Luo |
Efficient electro-thermal co-analysis on CPU+GPU heterogeneous architecture. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Takeshi Kida, Yasumasa Tsukamoto, Yuji Kihara |
Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Amith Singhee, Emrah Acar, Mohammad Imran Younus, Rama N. Singh, Aditya Bansal |
DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuexin Liu, Zao Liu, Sheldon X.-D. Tan, Joseph A. Gordon |
Full-chip thermal analysis of 3D ICs with liquid cooling by GPU-accelerated GMRES method. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mao-Yin Wang, Jen-Chieh Yeh |
Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Young-Joon Lee, Sung Kyu Lim |
Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ying Zhang, Lide Duan, Bin Li, Lu Peng |
Optimal microarchitectural design configuration selection for processor hard-error reliability. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand |
An accurate current source model for CMOS based combinational logic cell. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Haiqing Nan, Li Li, Ken Choi |
TDDB-based performance variation of combinational logic in deeply scaled CMOS technology. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Samatha Gummalla, Anupama R. Subramaniam, Yu Cao, Chaitali Chakrabarti |
An analytical approach to efficient circuit variability analysis in scaled CMOS design. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake |
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram B. Suresh, Wayne P. Burleson |
Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings |
Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shirish Bahirat, Sudeep Pasricha |
A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaloo Rakheja, Azad Naeemi |
Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi |
History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | G. K. Reddy, Kapil Jainwal, Jawar Singh, Saraju P. Mohanty |
Process variation tolerant 9T SRAM bitcell design. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Pinaki Chakrabarti, Vikram Bhatt, Dwight Hill, Aiqun Cao |
Clock mesh framework. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic |
A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujay Deb, Kevin Chang, Amlan Ganguly, Xinmin Yu, Christof Teuscher, Partha Pratim Pande, Deuk Hyoun Heo, Benjamin Belzer |
Design of an efficient NoC architecture using millimeter-wave wireless links. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma |
A novel robust signaling scheme for high-speed low-power communication over long wires. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Julian Garcia, Ana Rusu |
An extended-range incremental CT ∑Δ ADC with optimized digital filter. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijaya Kumar Gurugubelli, Shreepad Karmalkar |
A scalable curve-fit model of the substrate coupling resistances for IC design. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Meeta Srivastav, Michael B. Henry, Leyla Nazhandali |
Design of low-power, scalable-throughput systems at near/sub threshold voltage. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, Hiroaki Komatsu |
Speed-path analysis for multi-path failed latches with random variation. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohit Shah, Brian Mears, Chaitali Chakrabarti, Andreas Spanias |
A top-down design methodology using virtual platforms for concept development. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramamurthy Vishweshwara, Nagabhiru Mahita, Ramakrishnan Venkatraman |
Placement aware clock gate cloning and redistribution methodology. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruijing Shen, Sheldon X.-D. Tan, Xuexin Liu |
A new voltage binning technique for yield improvement based on graph theory. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Zigang Xiao, Martin D. F. Wong |
Algorithmic study on the routing reliability problem. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenchao Gao, Qiang Zhou, Xu Qian, Yici Cai |
A DyadicCluster method used for nonlinear placement. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthik Rajagopal |
Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
An enhanced debug-aware network interface for Network-on-Chip. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason G. Tong, Marc Bottle, Zeljko Zilic |
Assertion clustering for compacted test sequence generation. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong |
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin Shrivastava, Harindranath Parameswaran |
Efficient reduction techniques for statistical model generation of standard cells. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker |
TSV and DFT cost aware circuit partitioning for 3D-SOCs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey |
VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
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