| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman |
Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs.  |
ISVLSI  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Pranab Roy, Rajesh Mandal, Hafizur Rahaman, Parthasarathi Dasgupta |
A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang 0002, Wei Zhang 0012, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang |
A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fataneh Jafari, Mahdi Mosaffa, Siamak Mohammadi |
On the Potentials of FinFETs for Asynchronous Circuit Design. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | David Fuschelberger, Ioannis Pyrounakis, Tasos Dagiuklas, Nikolaos S. Voros, Carlos Ribeiro |
Next Generation Smart Home Systems Using Hardware Acceleration Techniques. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli |
A DRAM Centric NoC Architecture and Topology Design Approach. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Pande, Joseph Zambreno, Prasant Mohapatra |
Architectures for Simultaneous Coding and Encryption Using Chaotic Maps. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno |
Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthew Morrison, Nagarajan Ranganathan |
Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Zohre Mohammadi-Arfa, Ali Jahanian |
A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghavan Kumar, Vinay C. Patil, Sandip Kundu |
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir-Mohammad Rahmani, Khalid Latif 0002, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
Power-Efficient Inter-Layer Communication Architectures for 3D NoC. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumya J., Putta Venkatesh, Santanu Chattopadhyay |
Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti |
Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Buttrick, Sandip Kundu |
Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandan Karfa, Chitta Mandal, Dipankar Sarkar |
Verification of Register Transfer Level Low Power Transformations. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing Cao, Albert Nymeyer |
A Markov Performance Model for Buffered Protocol Design. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Han-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan |
Impact of Circuit Degradation on FPGA Design Security. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ansuman Banerjee |
Requirement Evolution Management: A Systematic Approach. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Harshit Agnihotri, Abhishek Ranjan, Pramod Kumar Tiwari, S. Jit |
An Analytical Drain Current Model for Short-Channel Triple-Material Double-Gate MOSFETs. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alpana Agarwal, Chandra Shekhar |
Synthesis of Analog IC Building Blocks. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Santosh Ghosh |
Design and Analysis of Pairing Based Cryptographic Hardware for Prime Fields. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik |
An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | D. S. Harish Ram, M. C. Bhuvaneswari, S. M. Logesh |
A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai |
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Florian Darve, Abbas Sheibanyrad, Pascal Vivet, Frédéric Pétrot |
Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | P. Rajshekar, M. Malathi |
Power Efficient Multiplexer Using DLDFF Synchronous Counter. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh C. Patil, S. Qureshi |
Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas G. Savva, Theocharis Theocharides, Vassos Soteriou |
Intelligent On/Off Link Management for On-chip Networks. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthias Kühnle, Alisson Vasconcelos De Brito, Christoph Roth, Konstantinos Dagas, Jürgen Becker |
The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan |
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | G. Indumathi, K. V. Ramakrishnan |
Study and Analysis of Power Optimization Techniques for Embedded Systems. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang 0012, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu |
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Khawas, Amitava Banerjee, Siddhartha Mukhopadhyay |
A Response Surface Method for Design Space Exploration and Optimization of Analog Circuits. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal |
Equivalence Checking of Array-Intensive Programs. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Evriklis Kounalakis, Christos P. Sotiriou, Vassilis Zebilis |
Statistical Timing-Based Post-Placement Leakage Recovery. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda |
500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti". |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan, Vijaykrishnan Narayanan |
Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Pradip Kumar Sahu, Putta Venkatesh, Sunilraju Gollapalli, Santanu Chattopadhyay |
Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinitha Arakkonam Palaniveloo, Arcot Sowmya |
Application of Formal Methods for System-Level Verification of Network on Chip. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu, Axel Jantsch |
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall |
Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Hongyan Zhang, Rolf Drechsler |
ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | |
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India |
ISVLSI |
2011 |
DBLP BibTeX RDF |
|
| 1 | Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal |
Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Adel Dokhanchi, Ali Jahanian, Esfandiar Mehrshahi, M. Taghi Teimoori |
Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | B. Sandeep Kumar, Vikram Pudi, K. Sridharan |
Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aman Gupta, Satyam Mandavalli, Vincent J. Mooney, Keck-Voon Ling, Arindam Basu, Henry Johan, Budianto Tandianus |
Low Power Probabilistic Floating Point Multiplier Design. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Varun Vasudevan, Vinay Sheshadri, Sivarama Krishnan R., Vasundara Patel K. S. |
Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli |
A Simulation Based Buffer Sizing Algorithm for Network on Chips. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepak Dasalukunte, Fredrik Rusek, John B. Anderson, Viktor Öwall |
Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier Systems. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ting-Feng Chang, Tsang-Chi Kan, Shih-Hsien Yang, Shanq-Jang Ruan |
Enhanced Redundant via Insertion with Multi-via Mechanisms. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anita Arvind Deshmukh, Raghevendra Deshmukh, Rajendra Patrikar |
Low Power Asynchronous Sigma-Delta Modulator Using Hysteresis Level Control. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab Khawas, Siddhartha Mukhopadhyay |
A Design of Experiment Based Approach to Variance Optimal Design of CMOS OpAmp. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas |
A Prefix Based Reconfigurable Adder. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Prafulla Galphade, Rasika Dhavse |
Modeling Study of Impact of Surface Roughness on Flicker Noise in MOSFET. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Garima Kapur, Kapil Bhola, C. M. Markan |
Design to Introduce On-chip Fine Tunability in Analog Active Inductor. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Arnab K. Biswas, A. Bulusu, S. Dasgupta |
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Charvi Dhoot, Vincent J. Mooney, Lap Pui Chau, Shubhajit Roy Chowdhury |
Low Power Motion Estimation with Probabilistic Computing. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rashmi K. Lomte, P. C. Bhaskar |
High Speed Convolution and Deconvolution Using Urdhva Triyagbhyam. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Tang, Shuai Wang, Jie S. Hu, Xiaobo Sharon Hu |
Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kameswar Rao Vaddina, Amir-Mohammad Rahmani, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila |
Thermal Analysis of Advanced 3D Stacked Systems. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang, Shenggang Chen |
AIFSP: An Adaptive Instruction Flow Stream Processor. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-I Chen, Juinn-Dar Huang |
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | B. N. B. Ray, Shankar Balachandran |
A New Wirelength Model for Analytical Placement. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | S. R. Sant, S. S. Waikar, Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma |
A 16-Gbps 9mW Transmitter with FFE in 90nm CMOS Technology for Off-Chip Communication. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mallikarjuna Rao Nimmagadda, Ajit Pal |
Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Behnam Ghavami, Mohsen Raji, Hossein Pedram |
Metallic-CNT and Non-uniform CNTs Tolerant Design of CNFET-based Circuits Using Independent N2-Transistor Structures. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Naveen Kumar Kancharapu, Marshnil Vipin Dave, Veerraju Masimukkula, Maryam Shojaei Baghini, Dinesh Kumar Sharma |
A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang |
Layer-Aware Design Partitioning for Vertical Interconnect Minimization. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini, Kamakoti Veezhinathan |
A Method for Integrating Network-on-Chip Topologies with 3D ICs. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay |
TSV-aware Scan Chain Reordering for 3D IC. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nishant Dhumane, Sudheendra K. Srivathsa, Sandip Kundu |
Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu |
On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis |
Gate Sizing Minimizing Delay and Area. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Avinash Lakshminarayana, Sumit Ahuja, Sandeep K. Shukla |
High Level Power Estimation Models for FPGAs. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Samarth Kaushik, Amit Kumar Singh, Thambipillai Srikanthan |
Preprocessing-Based Run-Time Mapping of Applications on NoC-based MPSoCs. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Manas Kumar Hati, Tarun Kanti Bhattacharyya |
Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan |
A Design Space Exploration Methodology for Application Specific MPSoC Design. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Babak Hidaji, Salar Alipour, Kasyab P. Subramaniyan, Per Larsson-Edefors |
Application-Specific Energy Optimization of General-Purpose Datapath Interconnect. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Santanu Kundu, Santanu Chattopadhyay |
Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lilia Zaourar, Yann Kieffer, Chouki Aktouf |
A Global Optimization for Scan Chain Insertion at the RT-level. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Weichen Liu, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Wei Zhang 0012, Mahdi Nikdast, Zhehui Wang |
A NoC Traffic Suite Based on Real Applications. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | R. K. Sharma, Aditi Sood |
Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Fault Detection and Repair. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | David Stevens, Vassilios Chouliaras |
LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel P. Volpato, Alexandre K. I. Mendonça, Luiz C. V. dos Santos, José Luís Güntzel |
A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos |
SUT-RNS Forward and Reverse Converters. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kapil K. Rajput, Anil K. Saini, Subash C. Bose |
DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Gamrat |
Challenges and Perspectives of Computer Architecture at the Nano Scale. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Khatir, Alireza Ejlali |
A Body Biasing Method for Charge Recovery Circuits: Improving the Energy Efficiency and DPA-Immunity. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahtab Niknahad, Michael Hübner, Jürgen Becker |
Reliability Analysis and Improvement in Nano Scale Design. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Romuald Girardey, Michael Hübner, Jürgen Becker |
Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hosseinabady, Jose Luis Nunez-Yanez, Antonio Marcello Coppola |
Task Dispersal Measurement in Dynamic Reconfigurable NoCs. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Elena Kakoulli, Vassos Soteriou, Theocharis Theocharides |
An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Zhang Hao, Shibin Tang |
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Lars Braun, Jürgen Becker |
Two-Dimensional Dynamic Multigrained Reconfigurable Hardware. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Imen Mansouri, Camille Jalier, Fabien Clermidy, Pascal Benoit, Lionel Torres |
Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ankit More, Baris Taskin |
Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | E. Vilella, Ángel Diéguez |
Design of a Bandgap Reference Circuit with Trimming for Operation at Multiple Voltages and Tolerant to Radiation in 90nm CMOS Technology. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
High-Performance TSV Architecture for 3-D ICs. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
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