Search results for "ITC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Dhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson	Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current.	ITC	2011	DBLP DOI BibTeX RDF
1	Jose Moreira	Development of an ATE test cell for at-speed characterization and production testing.	ITC	2011	DBLP DOI BibTeX RDF
1	Xinli Gu	The gap: Test challenges in Asia manufacturing field.	ITC	2011	DBLP DOI BibTeX RDF
1	Bailarico Balangue	In circuit test (ICT): The king is dead; long live the king!	ITC	2011	DBLP DOI BibTeX RDF
1	Urban Ingelsson, Bashir M. Al-Hashimi	Investigation into voltage and process variation-aware manufacturing test.	ITC	2011	DBLP DOI BibTeX RDF
1	Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji	DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management.	ITC	2011	DBLP DOI BibTeX RDF
1	Jing Zeng	Challenges and best practices in advanced silicon debug.	ITC	2011	DBLP DOI BibTeX RDF
1	Dragoljub Gagi Drmanac, Michael Laisne	Wafer probe test cost reduction of an RF/A device by automatic testset minimization - A case study.	ITC	2011	DBLP DOI BibTeX RDF
1	Ender Yilmaz, Sule Ozev, Kenneth M. Butler	Adaptive multidimensional outlier analysis for analog and mixed signal circuits.	ITC	2011	DBLP DOI BibTeX RDF
1	Wing Chiu Tam, R. D. (Shawn) Blanton	Physically-aware analysis of systematic defects in integrated circuits.	ITC	2011	DBLP DOI BibTeX RDF
1	Phil Nigh	Industry leaders panel - How will testing change in the next 10 years?	ITC	2011	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	On using address scrambling to implement defect tolerance in SRAMs.	ITC	2011	DBLP DOI BibTeX RDF
1	George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	A Software-Based Self-Test methodology for on-line testing of processor caches.	ITC	2011	DBLP DOI BibTeX RDF
1	Bram Kruseman, Bratislav Tasic, Camelia Hora, Jos Dohmen, Hamidreza Hashempour, Maikel van Beurden, Yizi Xing	Defect Oriented Testing for analog/mixed-signal devices.	ITC	2011	DBLP DOI BibTeX RDF
1	Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen	Design-for-debug layout adjustment for FIB probing and circuit editing.	ITC	2011	DBLP DOI BibTeX RDF
1	V. R. Devanathan, Srinivas Kumar Vooka	Techniques to improve memory interface test quality for complex SoCs.	ITC	2011	DBLP DOI BibTeX RDF
1	Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara	Faster-than-at-speed test for increased test quality and in-field reliability.	ITC	2011	DBLP DOI BibTeX RDF
1	Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu	Application of a continuous-time level crossing quantization method for timing noise measurements.	ITC	2011	DBLP DOI BibTeX RDF
1	Saeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng	End-to-end error correction and online diagnosis for on-chip networks.	ITC	2011	DBLP DOI BibTeX RDF
1	Aritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee	Accurate signature driven power conscious tuning of RF systems using hierarchical performance models.	ITC	2011	DBLP DOI BibTeX RDF
1	Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu	Lithography aware critical area estimation and yield analysis.	ITC	2011	DBLP DOI BibTeX RDF
1	Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen	Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing.	ITC	2011	DBLP DOI BibTeX RDF
1	Yiwen Shi, Kantapon Kaewtip, Wan-Chan Hu, Jennifer Dworak	Partial state monitoring for fault detection estimation.	ITC	2011	DBLP DOI BibTeX RDF
1	Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy	Low power compression utilizing clock-gating.	ITC	2011	DBLP DOI BibTeX RDF
1	Pankaj Pant, Eric Skeels	Hardware hooks for transition scan characterization.	ITC	2011	DBLP DOI BibTeX RDF
1	Zhaobo Zhang, Krishnendu Chakrabarty, Zhanglei Wang, Zhiyuan Wang, Xinli Gu	Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks.	ITC	2011	DBLP DOI BibTeX RDF
1	Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski	EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.	ITC	2011	DBLP DOI BibTeX RDF
1	Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang	A novel scan segmentation design method for avoiding shift timing failure in scan testing.	ITC	2011	DBLP DOI BibTeX RDF
1	Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab	A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.	ITC	2011	DBLP DOI BibTeX RDF
1	Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel	Evaluation of TSV and micro-bump probing for wide I/O testing.	ITC	2011	DBLP DOI BibTeX RDF
1	Dilip K. Bhavsar, Steve Poehlman	Test access and the testability features of the Poulson multi-core Intel Itanium® processor.	ITC	2011	DBLP DOI BibTeX RDF
1	Kenneth P. Parker, Shuichi Kameyama, David Dubberke	Surviving state disruptions caused by test: A case study.	ITC	2011	DBLP DOI BibTeX RDF
1	Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, M. Reese, J. Rearick, Jason Rivers	Cell-aware analysis for small-delay effects and production test results from different fault models.	ITC	2011	DBLP DOI BibTeX RDF
1	Bill Eklow, R. D. (Shawn) Blanton (eds.)	2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011	ITC	2011	DBLP BibTeX RDF
1	Masahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu	Real-time testing method for 16 Gbps 4-PAM signal interface.	ITC	2011	DBLP DOI BibTeX RDF
1	Abdullah Mumtaz, Michael E. Imhof, Hans-Joachim Wunderlich	P-PET: Partial pseudo-exhaustive test for high defect coverage.	ITC	2011	DBLP DOI BibTeX RDF
1	Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas	Optimal manufacturing flow to determine minumum operating voltage.	ITC	2011	DBLP DOI BibTeX RDF
1	Anne E. Gattiker, Phil Nigh	Using well/substrate bias manipulation to enhance voltage-test-based defect detection.	ITC	2011	DBLP DOI BibTeX RDF
1	Heiko Ehrenberg, Bob Russell	IEEE Std 1581 - A standardized test access methodology for memory devices.	ITC	2011	DBLP DOI BibTeX RDF
1	Liang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson	Transition test bring-up and diagnosis on UltraSPARCTM processors.	ITC	2011	DBLP DOI BibTeX RDF
1	A. M. Majid, David C. Keezer	Multi-function multi-GHz ATE extension using state-of-the-art FPGAs.	ITC	2011	DBLP DOI BibTeX RDF
1	Hsiu-Ming Chang, Kwang-Ting Cheng, Wangyang Zhang, Xin Li, Kenneth M. Butler	Test cost reduction through performance prediction using virtual probe.	ITC	2011	DBLP DOI BibTeX RDF
1	Kapil R. Gotkhindikar, W. Robert Daasch, Kenneth M. Butler, John M. Carulli Jr., Amit Nahar	Die-level adaptive test: Real-time test reordering and elimination.	ITC	2011	DBLP DOI BibTeX RDF
1	Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu	Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base.	ITC	2011	DBLP DOI BibTeX RDF
1	Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng	Deterministic IDDQ diagnosis using a net activation based model.	ITC	2011	DBLP DOI BibTeX RDF
1	Yasuhiro Takahashi, Akinori Maeda, Mitsuhiro Ogura	Actual implementation of multi domain test: Further reduction of cost of test.	ITC	2011	DBLP DOI BibTeX RDF
1	Bill Dally	Power, programmability, and granularity: The challenges of ExaScale computing.	ITC	2011	DBLP DOI BibTeX RDF
1	Ivo Koren, Ben Schuffenhauer, Frank Demmerle, Frank Neugebauer, Gert Pfahl, Dirk Rautmann	Multi-site test of RF transceivers on low-cost digital ATE.	ITC	2011	DBLP DOI BibTeX RDF
1	Stephen K. Sunter, Aubin Roy	Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan.	ITC	2011	DBLP DOI BibTeX RDF
1	Guihai Yan, Xiaowei Li	Online timing variation tolerance for digital integrated circuits.	ITC	2011	DBLP DOI BibTeX RDF
1	Kanad Basu, Prabhat Mishra, Priyadarsan Patra	Efficient combination of trace and scan signals for post silicon validation and debug.	ITC	2011	DBLP DOI BibTeX RDF
1	Siva Sudani, Minshun Wu, Degang Chen	A novel robust and accurate spectral testing method for non-coherent sampling.	ITC	2011	DBLP DOI BibTeX RDF
1	Enamul Amyeen, Andal Jayalakshmi, Srikanth Venkataraman, Sundar V. Pathy, Ewe C. Tan	Logic BIST silicon debug and volume diagnosis methodology.	ITC	2011	DBLP DOI BibTeX RDF
1	Jyuo-Min Shyu	A systems perspective on the R&D of industrial technology.	ITC	2011	DBLP DOI BibTeX RDF
1	Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li	Test clock domain optimization for peak power supply noise reduction during scan.	ITC	2011	DBLP DOI BibTeX RDF
1	Hideo Okawara	Elegant construction of SSC implemented signal by AWG and organized under-sampling of wideband signal.	ITC	2011	DBLP DOI BibTeX RDF
1	Mitchell Lin, Tyler Tolman	Analyzing ATE interconnect performance for serial links of 10 Gbps and above.	ITC	2011	DBLP DOI BibTeX RDF
1	Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir	Forward prediction based on wafer sort data - A case study.	ITC	2011	DBLP DOI BibTeX RDF
1	Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao	A fully cell-based design for timing measurement of memory.	ITC	2011	DBLP DOI BibTeX RDF
1	Brandon Noia, Krishnendu Chakrabarty	Pre-bond probing of TSVs in 3D stacked ICs.	ITC	2011	DBLP DOI BibTeX RDF
1	Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto	State of the art low capture power methodology.	ITC	2011	DBLP DOI BibTeX RDF
1	A. J. van de Goor, Said Hamdioui, Halil Kukner	Generic, orthogonal and low-cost March Element based memory BIST.	ITC	2011	DBLP DOI BibTeX RDF
1	Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz	Multiple fault activation cycle tests for transistor stuck-open faults.	ITC	2010	DBLP DOI BibTeX RDF
1	Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise	Low cost at-speed testing using On-Product Clock Generation compatible with test compression.	ITC	2010	DBLP DOI BibTeX RDF
1	Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday	Vendor-agnostic native compression engine.	ITC	2010	DBLP DOI BibTeX RDF
1	Koji Asami, Hiroyuki Miyajima, Tsuyoshi Kurosawa, Takenori Tateiwa, Haruo Kobayashi	Timing skew compensation technique using digital filter with novel linear phase condition.	ITC	2010	DBLP DOI BibTeX RDF
1	Jeffrey E. Nelson, Wing Chiu Tam, Ronald D. Blanton	Automatic classification of bridge defects.	ITC	2010	DBLP DOI BibTeX RDF
1	Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu	Modeling TSV open defects in 3D-stacked DRAM.	ITC	2010	DBLP DOI BibTeX RDF
1	Warin Sootkaneung, Kewal K. Saluja	On techniques for handling soft errors in digital circuits.	ITC	2010	DBLP DOI BibTeX RDF
1	Suri Basharapandiyan, Yi Cai	Practical active compensation techniques for ATE power supply response for testing of mixed signal data storage SOCs.	ITC	2010	DBLP DOI BibTeX RDF
1	Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang	Fault models and test methods for subthreshold SRAMs.	ITC	2010	DBLP DOI BibTeX RDF
1	Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer	Dynamic channel allocation for higher EDT compression in SoC designs.	ITC	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed	Is test power reduction through X-filling good enough?	ITC	2010	DBLP DOI BibTeX RDF
1	Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen	The scan-DFT features of AMD's next-generation microprocessor core.	ITC	2010	DBLP DOI BibTeX RDF
1	Timothy Daniel Lyons	Complete testing of receiver jitter tolerance.	ITC	2010	DBLP DOI BibTeX RDF
1	Kenneth Spargo	AXIe® 2.0 and MVP-C: Open ATE software standards.	ITC	2010	DBLP DOI BibTeX RDF
1	Michele Portolan, Bradford G. Van Treuren, Suresh Goyal	Scan chain securization though Open-Circuit Deadlocks.	ITC	2010	DBLP DOI BibTeX RDF
1	Luca Amati, Cristiana Bolchini, Fabio Salice, Federico Franzoso	Improving fault diagnosis accuracy by automatic test set modification.	ITC	2010	DBLP DOI BibTeX RDF
1	Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab	Low capture power at-speed test in EDT environment.	ITC	2010	DBLP DOI BibTeX RDF
1	Jim O'Reilly, Ajay Khoche, Ernst Wahl, Bruce R. Parnas	STIL P1450.4: A standard for test flow specification.	ITC	2010	DBLP DOI BibTeX RDF
1	Yu Zhang, Vishwani D. Agrawal	A diagnostic test generation system.	ITC	2010	DBLP DOI BibTeX RDF
1	Peter Wohl, John A. Waicukauski, T. Finklea	Increasing PRPG-based compression by delayed justification.	ITC	2010	DBLP DOI BibTeX RDF
1	Fan Yang, Sreejit Chakravarty	Testing of latch based embedded arrays using scan tests.	ITC	2010	DBLP DOI BibTeX RDF
1	Yu Huang 0005, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen	Case study of scan chain diagnosis and PFA on a low yield wafer.	ITC	2010	DBLP DOI BibTeX RDF
1	Wing Chiu Tam, Osei Poku, Ronald D. Blanton	Systematic defect identification through layout snippet clustering.	ITC	2010	DBLP DOI BibTeX RDF
1	Kun Young Chung, Sandeep K. Gupta	Design and test of latch-based circuits to maximize performance, yield, and delay test quality.	ITC	2010	DBLP DOI BibTeX RDF
1	Jingbo Duan, Le Jin, Degang Chen	A new method for estimating spectral performance of ADC from INL.	ITC	2010	DBLP DOI BibTeX RDF
1	V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar	Towards effective and compression-friendly test of memory interface logic.	ITC	2010	DBLP DOI BibTeX RDF
1	James Crafts, David Bogdan, Dennis Conti, Donato O. Forlenza, Orazio P. Forlenza, William V. Huott, Mary P. Kusko, Edward Seymour, Timothy Taylor, Brian Walsh	Testing the IBM Power 7™ 4 GHz eight core microprocessor.	ITC	2010	DBLP DOI BibTeX RDF
1	Ron Press, Erik H. Volkerink (eds.)	2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010	ITC	2010	DBLP BibTeX RDF
1	Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche	Path coverage based functional test generation for processor marginality validation.	ITC	2010	DBLP DOI BibTeX RDF
1	Mohammed A. Abdul-Aziz, Mehdi Baradaran Tahoori	Soft error reliability aware placement and routing for FPGAs.	ITC	2010	DBLP DOI BibTeX RDF
1	Koji Asami, Toshiaki Kurihara, Yushi Inada	Evaluation techniques of frequency-dependent I/Q imbalances in wideband quadrature mixers.	ITC	2010	DBLP DOI BibTeX RDF
1	Sara Karamati, Zainalabedin Navabi	Using context based methods for test data compression.	ITC	2010	DBLP DOI BibTeX RDF
1	Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara	RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.	ITC	2010	DBLP DOI BibTeX RDF
1	Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong	Mutation-based diagnostic test generation for hardware design error diagnosis.	ITC	2010	DBLP DOI BibTeX RDF
1	Deepa Mannath, Dallas Webster, Victor Montaño-Martinez, David Cohen, Shai Kush, Thiagarajan Ganesan, Adesh Sontakke	Structural approach for built-in tests in RF devices.	ITC	2010	DBLP DOI BibTeX RDF
1	Narendra Devta-Prasanna, Arun Gunda	Clock Gate Test Points.	ITC	2010	DBLP DOI BibTeX RDF
1	Ho Fai Ko, Nicola Nicolici	Automated trace signals selection using the RTL descriptions.	ITC	2010	DBLP DOI BibTeX RDF
1	S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu	Modeling the impact of process variation on resistive bridge defects.	ITC	2010	DBLP DOI BibTeX RDF