Search results for "Ilia Polian"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Philipp Jovanovic, Martin Kreuzer, Ilia Polian	A Fault Attack on the LED Block Cipher.	COSADE	2012	DBLP DOI BibTeX RDF
1	Alexandru Paler, Ilia Polian, John P. Hayes	Detection and diagnosis of faulty quantum circuits.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian	On the optimality of K longest path generation algorithm under memory constraints.	DATE	2012	DBLP BibTeX RDF
1	Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker	Modeling and Mitigating Transient Errors in Logic Circuits.	IEEE Trans. Dependable Sec. Comput.	2011	DBLP DOI BibTeX RDF
1	Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich	Variation-aware fault modeling.	SCIENCE CHINA Information Sciences	2011	DBLP DOI BibTeX RDF
1	Ilia Polian, John P. Hayes	Selective Hardening: Toward Cost-Effective Error Tolerance.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Matthias Sauer, Jie Jiang, Alejandro Czutro, Ilia Polian, Bernd Becker	Efficient SAT-Based Search for Longest Sensitisable Paths.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell	Towards Variation-Aware Test Methods.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Delay test, Adaptive test, Parameter variations
1	Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes	Tomographic Testing and Validation of Probabilistic Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Probabilistic testing, quantum computing
1	Philipp Klaus Krause, Ilia Polian	Adaptive voltage over-scaling for resilient applications.	DATE	2011	DBLP BibTeX RDF
1	Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker	SAT-based analysis of sensitisable paths.	DDECS	2011	DBLP DOI BibTeX RDF
1	Matthias Sauer, V. Tomashevich, J. Muller, Matthew D. T. Lewis, A. Spilla, Ilia Polian, Bernd Becker, W. Burgard	An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker	Estimation of component criticality in early design steps.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker	Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.	International Journal of Parallel Programming	2010	DBLP DOI BibTeX RDF
1	Ilia Polian	Power Supply Noise: Causes, Effects, and Testing.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker	Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien).	it - Information Technology	2010	DBLP DOI BibTeX RDF
1	Ilia Polian, John P. Hayes	Advanced modeling of faults in Reversible circuits.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich	Variation-Aware Fault Modeling.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Ilia Polian	Special session 4B: Panel low-power test and noise-aware test: Foes or friends?	VTS	2010	DBLP DOI BibTeX RDF
1	Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian	SUPERB: Simulator utilizing parallel evaluation of resistive bridges.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PPSFP, SPPFP, fault mapping, Resistive bridging faults, bridging fault simulation
1	Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker	Dynamic Compaction in SAT-Based ATPG.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Kunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker	Reducing temperature variability by routing heat pipes.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reliability, physical design, thermal modeling, thermal simulation
1	Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker	An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.	VTS	2009	DBLP DOI BibTeX RDF
1	Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker	TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru Eles, Zebo Peng	Analysis and optimization of fault-tolerant embedded systems with hardened processors.	DATE	2009	DBLP BibTeX RDF
1	Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker	ATPG-based grading of strong fault-secureness.	IOLTS	2009	DBLP DOI BibTeX RDF
1	Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker	On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng	Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.	ITC	2008	DBLP DOI BibTeX RDF
1	Ilia Polian, Sudhakar M. Reddy, Bernd Becker	Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Damian Nowroth, Ilia Polian, Bernd Becker	A study of cognitive resilience in a JPEG compressor.	DSN	2008	DBLP DOI BibTeX RDF
1	Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker	Selective Hardening in Early Design Steps.	European Test Symposium	2008	DBLP DOI BibTeX RDF	Soft error mitigation, reliability
1	Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker	A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.	European Test Symposium	2008	DBLP DOI BibTeX RDF	Small-delay defects, resistive opens, probabilistic fault coverage, bridging fault simulation
1	Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng	Automatic Test Pattern Generation for Interconnect Open Defects.	VTS	2008	DBLP DOI BibTeX RDF	Interconnect opens, Open-via defects, ATPG
1	Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker	Resistive Bridging Fault Simulation of Industrial Circuits.	DATE	2008	DBLP DOI BibTeX RDF
1	Ilia Polian, Wenjing Rao	Selective Hardening of NanoPLA Circuits.	DFT	2008	DBLP DOI BibTeX RDF
1	Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker	On Reducing Circuit Malfunctions Caused by Soft Errors.	DFT	2008	DBLP DOI BibTeX RDF
1	Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen	Diagnosis of Realistic Defects Based on the X-Fault Model.	DDECS	2008	DBLP DOI BibTeX RDF
1	Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, O. Paul, Ilia Polian, R. Roth, K. Seitz, P. Ruther	Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors	CoRR	2007	DBLP BibTeX RDF
1	Ilia Polian, Alejandro Czutro, Bernd Becker	Evolutionary Optimization in Code-Based Test Compression	CoRR	2007	DBLP BibTeX RDF
1	Ilia Polian, Hideo Fujiwara	Functional Constraints vs. Test Compression in Scan-Based Delay Testing.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Overtesting prevention, Scan-based delay test, Test compression, Functional constraints
1	Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker	Power Droop Testing.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	power droop, signal integrity errors, high-frequency effects, low-frequency effects, ATPG, heuristic method, D-algorithm
1	John P. Hayes, Ilia Polian, Bernd Becker	An Analysis Framework for Transient-Error Tolerance.	VTS	2007	DBLP DOI BibTeX RDF
1	Ilia Polian, Damian Nowroth, Bernd Becker	Identification of Critical Errors in Imaging Applications.	IOLTS	2007	DBLP DOI BibTeX RDF	Low-cost on-line test, Selective hardening, Imaging applications, Error tolerance
1	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Simulating Resistive-Bridging and Stuck-At Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke	X-masking during logic BIST and its impact on defect coverage.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich	DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).	it - Information Technology	2006	DBLP DOI BibTeX RDF
1	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Automatic Test Pattern Generation for Resistive Bridging Faults.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	resistive short defects, ATPG, SAT, bridging faults
1	Ilia Polian, Hideo Fujiwara	Functional constraints vs. test compression in scan-based delay testing.	DATE	2006	DBLP DOI BibTeX RDF	overtesting prevention, scan-based delay test, test compression, functional constraints
1	Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara	Low-Cost Hardening of Image Processing Applications Against Soft Errors.	DFT	2006	DBLP DOI BibTeX RDF
1	Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm	Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.	DDECS	2006	DBLP BibTeX RDF
1	Sandip Kundu, Ilia Polian	An Improved Technique for Reducing False Alarms Due to Soft Errors.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Jan Reineke, Björn Wachter, Stephan Thesing, Reinhard Wilhelm, Ilia Polian, Jochen Eisinger, Bernd Becker	A Definition and Classification of Timing Anomalies.	WCET	2006	DBLP BibTeX RDF
1	Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker	Power Droop Testing.	ICCD	2006	DBLP BibTeX RDF
1	Ilia Polian	Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications).	it - Information Technology	2005	DBLP DOI BibTeX RDF
1	Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker	Modeling Feedback Bridging Faults with Non-Zero Resistance.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	feedback bridging faults, resistive bridging faults, bridging fault simulation
1	Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker	Transient fault characterization in dynamic noisy environments.	ITC	2005	DBLP DOI BibTeX RDF
1	Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker	On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	Temperature testing, Resistive defects, Early-life failures, Low-voltage testing
1	Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes	A Family of Logical Fault Models for Reversible Circuits.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	ATPG, fault models, quantum circuits, reversible circuits
1	Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker	Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.	VTS	2005	DBLP DOI BibTeX RDF	Deep submicron technology modeling, Resistive bridging faults
1	Ilia Polian, Alejandro Czutro, Bernd Becker	Evolutionary Optimization in Code-Based Test Compression.	DATE	2005	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker	Scalable Delay Fault BIST for Use with Low-Cost ATE.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	thermal constraints, BIST, SAT, delay testing, IP cores, symbolic methods
1	Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker	X-Masking During Logic BIST and Its Impact on Defect Coverage.	ITC	2004	DBLP DOI BibTeX RDF	X-Masking, Resistive Bridging Faults, Defect Coverage, Logic BIST
1	John P. Hayes, Ilia Polian, Bernd Becker	Testing for Missing-Gate Faults in Reversible Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	missing gate faults, fault models, design for test, quantum circuits, Reversible circuits
1	Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker	The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.	VTS	2004	DBLP DOI BibTeX RDF	Very-Low-Voltage testing, Resistive short defects
1	Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker	Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	fault simulation, crosstalk, industrial experiences, defect-based testing
1	Ilia Polian, Bernd Becker	Multiple Scan Chain Design for Two-Pattern Testing.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	scan chain insertion, delay testing, design for test, core-based test
1	Ilia Polian, Wolfgang Günther, Bernd Becker	Pattern-based verification of connections to intellectual property cores.	Integration	2003	DBLP DOI BibTeX RDF
1	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Simulating Resistive Bridging and Stuck-At Faults.	ITC	2003	DBLP DOI BibTeX RDF	Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation
1	Ilia Polian, Bernd Becker	Reducing ATE Cost in System-on-Chip Test.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Ilia Polian, Bernd Becker, Sudhakar M. Reddy	Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST.	DATE	2003	DBLP DOI BibTeX RDF
1	Ilia Polian, Irith Pomeranz, Bernd Becker	Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	n-detection, BDDs, formal techniques, Fault dominance
1	Ilia Polian, Piet Engelke, Bernd Becker	Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	Voting models, Fault simulation, Bridging faults
1	Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker	Sequential n -Detection Criteria: Keep It Simple. (PDF / PS)	IOLTW	2002	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker	Stop & Go BIST.	IOLTW	2002	DBLP DOI BibTeX RDF	Thermal constraints, BIST, Delay testing, IP cores
1	Ilia Polian, Wolfgang Günther, Bernd Becker	Efficient Pattern-Based Verification of Connections to IP Cores .	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker	Multiple Scan Chain Design for Two-Pattern Testing.	VTS	2001	DBLP DOI BibTeX RDF	Scan chain insertion, Delay testing, Design for test, Core-based test

Publications of "Ilia Polian" ( http://dblp.L3S.de/Authors/Ilia_Polian )