Search results for "Ing-Jer Huang"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Chi-Tsai Yeh, Chun-Hao Wang, Ing-Jer Huang, Weng-Fai Wong	Internet-based hardware/software co-design framework for embedded 3D graphics applications.	EURASIP J. Adv. Sig. Proc.	2011	DBLP DOI BibTeX RDF
1	Chun-Hung Lai, Fu-Ching Yang, Ing-Jer Huang	A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao, Ing-Jer Huang	An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Liang-Bi Chen, Yen-Ling Chen, Ing-Jer Huang	A Real-Time Power Analysis Platform for Power-Aware Embedded System Development.	J. Inf. Sci. Eng.	2011	DBLP BibTeX RDF
1	Liang-Bi Chen, Jiun-Cheng Ju, Chien-Chou Wang, Ing-Jer Huang	HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang	A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang	An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Liang-Bi Chen, Chi-Tsai Yeh, Hung-Yu Chen, Ing-Jer Huang	A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Chun-Hung Lai, Fu-Ching Yang, Chung-Fu Kao, Ing-Jer Huang	A trace-capable instruction cache for cost efficient real-time program trace compression in SoC.	DAC	2009	DBLP DOI BibTeX RDF	real time, cache, compression, program trace
1	Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang	An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang	A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang	A Reverse-encoding-based On-chip AHB Bus Tracer Supporting both Post-T and Pre-T Trace.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang	Automatic Verification of External Interrupt Behaviors for Microprocessor Design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Chung-Fu Kao, Hsin-Ming Chen, Ing-Jer Huang	Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	Yi-Ting Lin, Wen-Chi Shiue, Ing-Jer Huang	A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer.	DAC	2008	DBLP DOI BibTeX RDF	AMBA AHB, backward trace, bus tracer, circular buffer, forward trace, compression
1	Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang	Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yi-Ting Lin, Chien-Chou Wang, Ing-Jer Huang	AMBA AHB bus potocol checker with efficient debugging mechanism.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Chung-Ping Young, Chung-Chu Chia, Liang-Bi Chen, Ing-Jer Huang	NCPA: A Scheduling Algorithm for Multi-cipher and Multi-mode Reconfigurable Cryptosystem.	IIH-MSP	2008	DBLP DOI BibTeX RDF	multiple cipher, scheduling algorithm, Cryptosystem, operation mode, crypto-coprocessor
1	Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang	Verifying external interrupts of embedded microprocessor in SoC with on-chip bus.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin	An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration.	DAC	2007	DBLP DOI BibTeX RDF
1	Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang	Automatic Verification of External Interrupt Behaviors for Microprocessor Design.	DAC	2007	DBLP DOI BibTeX RDF
1	Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang	Configurable AMBA On-Chip Real-Time Signal Tracer.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Fu-Ching Yang, Ing-Jer Huang	An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools.	ASP-DAC	2007	DBLP DOI BibTeX RDF	16 bit, ARM7 software tools, THUMB instruction set microprocessor, short-precision computing
1	Tse-Chen Yeh, Tsung-Yu Ho, Hung-Yu Chen, Ing-Jer Huang	SystemC-Based Design Space Exploration of a 3D Graphics Acceleration SoC for Consumer Electronics.	EUC	2007	DBLP DOI BibTeX RDF	SystemC modeling, 3D graphics SoC, design space exploration, transaction-level modeling
1	Liang-Bi Chen, Ching-Chi Hu, Yen-Ling Chen, Chi-Wei Chu, Ing-Jer Huang	The AES Design Space Exploration with a Soft IP Generator.	IIH-MSP	2007	DBLP DOI BibTeX RDF
1	Liang-Bi Chen, Ing-Jer Huang, Yuan-Long Jeang	Design of a Dynamic PCM Selector for Non-deterministic Environment.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Wen-Kai Huang, I-Ting Lin, Shi-Wei Chen, Ing-Jer Huang	A cost-effective media processor for embedded applications [audio decoder example].	ISCAS	2005	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Dao-Zhen Chen	Mining Correlations of Human Gene Expression from Digital Gene Expression Profiles.	J. Inf. Sci. Eng.	2003	DBLP BibTeX RDF
1	Ing-Jer Huang, Dao-Zhen Chen	Automatic Assembly Program Retargeting for Micrco controllers.	J. Inf. Sci. Eng.	2003	DBLP BibTeX RDF
1	Ing-Jer Huang, Ping-Huei Xie	Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan, Tai-An Lu	A Retargetable Embedded In-Circuit Emulation Module for Microprocessors.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Ing-Jer Huang	Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	compiler instruction optimization, instruction set processor, pipeline hazards, pipeline taxonomy, synthesis
1	Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen	Parameterized MAC unit implementation.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Hsin-Ming Chen, Chung-Fu Kao	Reusable embedded in-circuit emulator.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Wen-Fu Kao	A Machine State Transition Approach to Instruction Retargeting for Embedded Microprocessors.	Design Autom. for Emb. Sys.	2000	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Dao-Zhen Chen	A new approach to assembly software retargeting for microcontrollers.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Li-Rong Wang	Automatic Simulation and Verification of Pipelined Microcontrollers.	J. Inf. Sci. Eng.	1999	DBLP BibTeX RDF
1	Ing-Jer Huang, Tai-An Lu	ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers.	DAC	1999	DBLP DOI BibTeX RDF
1	Ing-Jer Huang	A Case Study: Synthesis and Exploration of Instruction Set Design for Application-Specific Symbolic Computing.	J. Inf. Sci. Eng.	1998	DBLP BibTeX RDF
1	Ing-Jer Huang, Ping-Huei Xie	Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation. (PDF / PS)	ISSS	1998	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Alvin M. Despain	Synthesis of application specific instruction sets.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Alvin M. Despain	Synthesis of Instruction Sets for Pipelined Microprocessors.	DAC	1994	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Alvin M. Despain	Generating instruction sets and microarchitectures from applications.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Alvin M. Despain	An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors.	MICRO	1993	DBLP DOI BibTeX RDF	compiler back-end generation, hardware/software tradeoffs, inter-instruction dependency, pipeline hazard resolution, high level synthesis
1	Ing-Jer Huang, Alvin M. Despain	Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain	Application-Driven Design Automation for Microprocessor Design.	DAC	1992	DBLP DOI BibTeX RDF
1	Ing-Jer Huang, Alvin M. Despain	High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers.	DAC	1992	DBLP BibTeX RDF

Publications of "Ing-Jer Huang" ( http://dblp.L3S.de/Authors/Ing-Jer_Huang )