Search results for "Instruction scheduling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Muhammad Umar Farooq, Lizy K. John	Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures.	CC	2009	DBLP DOI BibTeX RDF	tiled dataflow architectures, operand network latency, instruction scheduling, resource contention
3	Ghassan Shobaki, Kent D. Wilken, Mark Heffernan	Optimal trace scheduling using enumeration.	TACO	2009	DBLP DOI BibTeX RDF	branch-and-bound enumeration, global instruction scheduling, optimal instruction scheduling, compiler optimizations, instruction-level parallelism, Instruction scheduling, trace scheduling
3	Abid M. Malik, Tyrel Russell, Michael Chase, Peter van Beek	Learning heuristics for basic block instruction scheduling.	J. Heuristics	2008	DBLP DOI BibTeX RDF	List scheduling heuristics, Machine learning, Instruction scheduling
3	Guilherme Ottoni, David I. August	Communication optimizations for global multi-threaded instruction scheduling.	ASPLOS	2008	DBLP DOI BibTeX RDF	graph min-cut, communication, synchronization, data-flow analysis, multi-threading, instruction scheduling
3	Shu Xiao, Edmund Ming-Kit Lai	VLIW instruction scheduling for minimal power variation.	TACO	2007	DBLP DOI BibTeX RDF	power variation reduction, Instruction scheduling, VLIW processors
3	Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Energy-efficient dynamic instruction scheduling logic through instruction grouping.	ISLPED	2006	DBLP DOI BibTeX RDF	instruction grouping, issue queue, dynamic instruction scheduling
3	Martha Mercaldi, Steven Swanson, Andrew Petersen, Andrew Putnam, Andrew Schwerin, Mark Oskin, Susan J. Eggers	Instruction scheduling for a tiled dataflow architecture.	ASPLOS	2006	DBLP DOI BibTeX RDF	instruction scheduling, dataflow, tiled architectures
3	Zhong Wang, Xiaobo Sharon Hu	Energy-aware variable partitioning and instruction scheduling for multibank memory architectures.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Multiple memory banks, nonorthogonal architecture, parallelism and serialism balance, runtime and energy saving tradeoff, instruction scheduling, operating mode
3	Mark Heffernan, Kent D. Wilken	Data-Dependency Graph Transformations for Instruction Scheduling.	J. Scheduling	2005	DBLP DOI BibTeX RDF	compiler scheduling, graph transformation, instruction scheduling, optimal scheduling
3	Gang Wang, Wenrui Gong, Ryan Kastner	Instruction scheduling using MAX-MIN ant system optimization.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	MAX-MIN ant system, instruction scheduling, list scheduling, force-directed scheduling
3	Amisha Parikh, Soontae Kim, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Instruction Scheduling for Low Power.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	energy simulators, energy, instruction scheduling, low-power systems
3	Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai	Compiler optimization on VLIW instruction scheduling for low power.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	VLIW instruction scheduling, instruction bus optimizations, low-power optimization, Compilers
3	Madhavi Gopal Valluri, R. Govindarajan	Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods
3	Toshinori Sato	A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism.	EUROMICRO	1999	DBLP DOI BibTeX RDF	instruction reissue, instruction window design, instruction level parallelism, data speculation, dynamic instruction scheduling
3	Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura	Instruction Scheduling for Power Reduction in Processor-Based System Design.	DATE	1998	DBLP DOI BibTeX RDF	Caches, Low-Power Design, Instruction Scheduling
3	David A. Dunn, Wei-Chung Hsu	Instruction Scheduling for the HP PA-8000.	MICRO	1996	DBLP BibTeX RDF	HP PA-8000, instruction polarity cache interfaces, memory dependences, production compiler, scheduling, latency, compiler optimization, instruction scheduling, resource constraints, micro-architecture
3	Roger Collins, Gordon Steven	Instruction Scheduling for a Superscalar Architecture.	EUROMICRO	1996	DBLP DOI BibTeX RDF	compile-time instruction scheduling, conditional group scheduler, HSA processor model, guarded instruction execution, instruction squashing, instruction buffer, performance evaluation, superscalar processors, superscalar architecture, functional units, branch instructions
2	Hui Wang, Rama Sangireddy, Sandeep Baldawa	Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors.	IEEE Trans. Parallel Distrib. Syst.	2009	DBLP DOI BibTeX RDF
2	Meikang Qiu, Lei Zhang, Edwin Hsing-Mean Sha	ILP optimal scheduling for multi-module memory.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	variable assignment, integer linear programming, energy saving, instruction scheduling
2	Peter Rounce, Alberto Ferreira de Souza	Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Simultaneous multi-threading, Wide issue architectures, VLIW, Dynamic instruction scheduling
2	Shu Xiao, Edmund Ming-Kit Lai	A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors.	IEEE Transactions on Signal Processing	2008	DBLP DOI BibTeX RDF
2	Toshinori Sato, Shingo Watanabe	Instruction Scheduling for Variation-Originated Variable Latencies.	ISQED	2008	DBLP DOI BibTeX RDF	variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations
2	Jean-Baptiste Tristan, Xavier Leroy	Formal verification of translation validators: a case study on instruction scheduling optimizations.	POPL	2008	DBLP DOI BibTeX RDF	the coq proof assistant, translation validation, scheduling optimizations, verified compilers
2	Abid M. Malik, Michael Chase, Tyrel Russell, Peter van Beek	An Application of Constraint Programming to Superblock Instruction Scheduling.	CP	2008	DBLP DOI BibTeX RDF
2	Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan, Todd C. Mowry	Compiler and hardware support for reducing the synchronization of speculative threads.	TACO	2008	DBLP DOI BibTeX RDF	automatic parallelization, instruction scheduling, Thread-level speculation, chip-multiprocessing
2	Guilherme Ottoni, David I. August	Global Multi-Threaded Instruction Scheduling.	MICRO	2007	DBLP DOI BibTeX RDF
2	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	The Molen compiler for reconfigurable processors.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	FPGA, reconfigurable computing, Instruction scheduling
2	Dae-Hwan Kim, Hyuk-Jae Lee	Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors.	SAMOS	2006	DBLP DOI BibTeX RDF
2	Jan Müller	Generalised Resource Model for Parallel Instruction Scheduling.	PARELEC	2006	DBLP DOI BibTeX RDF
2	Abid M. Malik, Jim McInnes, Peter van Beek	Optimal Basic Block Instruction Scheduling for Multiple-Issue Processors Using Constraing Programming.	ICTAI	2006	DBLP DOI BibTeX RDF
2	Tzong-Yen Lin, Rong-Guey Chang	Power-Aware Instruction Scheduling.	EUC	2006	DBLP DOI BibTeX RDF
2	Vikki Tang, Joran Siu, Alexander Vasilevskiy, Marcel Mitran	A framework for reducing instruction scheduling overhead in dynamic compilers.	CASCON	2006	DBLP DOI BibTeX RDF
2	Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie	Bypass aware instruction scheduling for register file power reduction.	LCTES	2006	DBLP DOI BibTeX RDF	architecture-sensitive compiler, bypass-sensitive, forwarding paths, operation table, processor bypasses, reservation table, power consumption, register file
2	Khaing Khaing Kyi Win, Weng-Fai Wong	Cooperative Instruction Scheduling with Linear Scan Register Allocation.	HiPC	2005	DBLP DOI BibTeX RDF
2	Joseph J. Sharkey, Dmitry V. Ponomarev	Non-uniform Instruction Scheduling.	Euro-Par	2005	DBLP DOI BibTeX RDF
2	Shu Xiao, Edmund Ming-Kit Lai, A. Benjamin Premkumar	Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
2	Shu Xiao, Edmund Ming-Kit Lai	Instruction scheduling of VLIW architectures for balanced power consumption.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	Instruction Scheduling for Dynamic Hardware Configurations.	DATE	2005	DBLP DOI BibTeX RDF
2	Arnab Roy 0001, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti	A framework for systematic validation and debugging of pipeline simulators.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Simulation-based verification, dataflow equivalence, pipeline validation, design space exploration, instruction scheduling, pipelined architectures
2	Fernanda Kri, Marc Feeley	Genetic Instruction Scheduling and Register Allocation.	SCCC	2004	DBLP DOI BibTeX RDF
2	Zhong Wang, Xiaobo Sharon Hu	Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks.	DATE	2004	DBLP DOI BibTeX RDF
2	John Cavazos, J. Eliot B. Moss	Inducing heuristics to decide whether to schedule.	PLDI	2004	DBLP DOI BibTeX RDF	Jikes RVM, Java, machine learning, supervised learning, compiler optimization, instruction scheduling
2	Sriraman Tallam, Xiangyu Zhang, Rajiv Gupta	Extending Path Profiling across Loop Backedges and Procedure Boundaries.	CGO	2004	DBLP DOI BibTeX RDF	overlapping path profiles, profile guided optimization and instruction scheduling, path profiles
2	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Register Constrained Modulo Scheduling.	IEEE Trans. Parallel Distrib. Syst.	2004	DBLP DOI BibTeX RDF	Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code
2	Dong-yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, Chengyong Wu, Roy Dz-Ching Ju	Efficient Resource Management during Instruction Scheduling for the EPIC Architecture.	IEEE PACT	2003	DBLP DOI BibTeX RDF
2	Jack Liu, Fred C. Chow, Timothy Kong, Rupan Roy	Variable Instruction Set Architecture and Its Compiler Support.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling
2	Enric Gibert, F. Jesús Sánchez, Antonio González	Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.	MICRO	2002	DBLP DOI BibTeX RDF
2	Josep M. Codina, Josep Llosa, Antonio González	A comparative study of modulo scheduling techniques.	ICS	2002	DBLP DOI BibTeX RDF	instruction level parallel architectures, instruction scheduling, Modulo scheduling, comparative study, quantitative evaluation
2	Christoph W. Keßler, Andrzej Bednarski	Optimal integrated code generation for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection
2	Sunghyun Jee, Kannappan Palaniappan	Performance evaluation for a compressed-VLIW processor.	SAC	2002	DBLP DOI BibTeX RDF	CVLIW processor, individual instruction scheduling, VLIW, ILP
2	Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori	A high-speed dynamic instruction scheduling scheme for superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
2	Mary D. Brown, Jared Stark, Yale N. Patt	Select-free instruction scheduling logic.	MICRO	2001	DBLP DOI BibTeX RDF
2	Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose	Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.	MICRO	2001	DBLP DOI BibTeX RDF	energy-efficient datapath, superscalar processor, power reduction, dynamic instruction scheduling
2	David Gregg	Comparing Tail Duplication with Compensation Code in Single Path Global Instruction Scheduling.	CC	2001	DBLP DOI BibTeX RDF
2	Peter van Beek, Kent D. Wilken	Fast Optimal Instruction Scheduling for Single-Issue Processors with Arbitrary Latencies.	CP	2001	DBLP DOI BibTeX RDF
2	Daniel Kästner, Sebastian Winkel	ILP-based Instruction Scheduling for IA-64.	LCTES/OM	2001	DBLP DOI BibTeX RDF
2	Christoph W. Keßler, Andrzej Bednarski	A Dynamic Programming Approach to Optimal Integrated Code Generation.	LCTES/OM	2001	DBLP DOI BibTeX RDF	integrated code generation, time profile, dynamic programming, register allocation, instruction scheduling, instruction selection
2	Amisha Parikh, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Energy-Aware Instruction Scheduling.	HiPC	2000	DBLP DOI BibTeX RDF
2	Kent D. Wilken, Jack Liu, Mark Heffernan	Optimal instruction scheduling using integer programming.	PLDI	2000	DBLP DOI BibTeX RDF
2	Rainer Leupers	Instruction Scheduling for Clustered VLIW DSPs.	IEEE PACT	2000	DBLP DOI BibTeX RDF
2	F. Jesús Sánchez, Antonio González	Instruction Scheduling for Clustered VLIW Architectures.	ISSS	2000	DBLP DOI BibTeX RDF
2	Hui Wu, Joxan Jaffar, Roland H. C. Yap	Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies.	CP	2000	DBLP DOI BibTeX RDF
2	Alberto Ferreira de Souza, Peter Rounce	On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	DTSVLIW, VLIW, Instruction scheduling
2	Toshinori Sato	Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure.	Euro-Par	1999	DBLP DOI BibTeX RDF
2	Patricia Borensztejn, Cristina Barrado, Jesús Labarta	Influence of Variable Time Operations in Static Instruction Scheduling.	Euro-Par	1999	DBLP DOI BibTeX RDF
2	Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors.	LCPC	1999	DBLP DOI BibTeX RDF
2	Matthew Arnold, Michael S. Hsiao, Ulrich Kremer, Barbara G. Ryder	Instruction Scheduling in the Presence of Java's Runtime Exceptions.	LCPC	1999	DBLP DOI BibTeX RDF
2	Lori Carter, Beth Simon, Brad Calder, Larry Carter, Jeanne Ferrante	Predicated Static Single Assignment.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Predicated Compiler Analysis, Instruction Scheduling
2	Rajiv Gupta	A Code Motion Framework for Global Instruction Scheduling.	CC	1998	DBLP DOI BibTeX RDF
2	David A. Berson, Rajiv Gupta, Mary Lou Soffa	Integrated Instruction Scheduling and Register Allocation Techniques.	LCPC	1998	DBLP DOI BibTeX RDF
2	Keith D. Cooper, Philip J. Schielke	Non-local Instruction Scheduling with Limited Code Growth.	LCTES	1998	DBLP DOI BibTeX RDF
2	Allen Leung, Krishna V. Palem, Amir Pnueli	A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Compiler-optimizations, instruction level parallelism, instruction scheduling, embedded applications
2	Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic	The Multicluster Architecture: Reducing Cycle Time Through Partitioning.	MICRO	1997	DBLP BibTeX RDF	partitioned architecture, static instruction scheduling, register allocation, decentralized architecture
2	Sebastian Schmidt	Global Instruction Scheduling - a Practical Approach.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
2	Michael E. Wolf, Dror E. Maydan, Ding-Kai Chen	Combining Loop Transformations Considering Caches and Scheduling.	MICRO	1996	DBLP BibTeX RDF	cache tiling, fission, loop interchange, outer loop unrolling, fusion, instruction scheduling
2	Larry Carter, Jeanne Ferrante, Susan Flynn Hummel	Hierarchical tiling for improved superscalar performance. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	hierarchical tiling, superscalar performance, inner-loop performance, compiler phases, scalar replacement, storage mapping, superscalar pipelined processors, automatic preprocessor, performance evaluation, parallel processing, parallelization, message passing, message passing, register allocation, instruction scheduling, optimizing compiler, data locality, archival storage
2	Raymond Lo, Sun Chan, Fred C. Chow, Shin-Ming Liu	Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution.	MICRO	1994	DBLP DOI BibTeX RDF	MIPS R8000, global instruction distribution, multiple-issue processors, processor resource utilization, MIPS R8000, instruction scheduling, code optimization
2	Ali-Reza Adl-Tabatabai, Thomas R. Gross	Detection and Recovery of Endangered Variables Caused by Instruction Scheduling.	PLDI	1993	DBLP DOI BibTeX RDF
2	Shlomit S. Pinter	Register Allocation with Instruction Scheduling: A New Approach.	PLDI	1993	DBLP DOI BibTeX RDF
2	Mark Smotherman, Shuchi Chawla II, Stan Cox, Brian A. Malloy	Instruction scheduling for the Motorola 88110.	MICRO	1993	DBLP DOI BibTeX RDF	MC88110, cache alignment, instruction scheduling, superscalar processors
2	Krishna V. Palem, Barbara B. Simons	Scheduling Time-Critical Instructions on RISC Machines.	ACM Trans. Program. Lang. Syst.	1993	DBLP DOI BibTeX RDF	RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor
2	Vicki H. Allan, Bogong Su, Pantung Wijaya, Jian Wang	Foresighted Instruction Scheduling Under Timing Constraints.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	foresighted instruction scheduling, minimum timing information, foresighted compaction, data dependency graph arcs, data dependency information, maximum timing information, greedy compaction algorithms, scheduling, parallel algorithms, parallel programming, graph theory, timing constraints, programming theory, list scheduling, look ahead
2	M. Anton Ertl, Andreas Krall	Optimal Instruction Scheduling using Constraint Logic Programming.	PLILP	1991	DBLP DOI BibTeX RDF
1	Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jörg Henkel	RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Lei Zhang, Meikang Qiu, Edwin Hsing-Mean Sha, Qingfeng Zhuge	Variable assignment and instruction scheduling for processor with multi-module memory.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Jiin Park, Jinhyung Park, Wonjoon Song, Songwook Yoon, Bernd Burgstaller, Bernhard Scholz	Treegraph-based Instruction Scheduling for Stack-based Virtual Machines.	Electr. Notes Theor. Comput. Sci.	2011	DBLP DOI BibTeX RDF
1	Xuemeng Zhang, Hui Wu, Jingling Xue	An efficient heuristic for instruction scheduling on clustered vliw processors.	CASES	2011	DBLP DOI BibTeX RDF
1	Stefan Brunthaler	Interpreter Instruction Scheduling.	CC	2011	DBLP DOI BibTeX RDF
1	Choonki Jang, Jungwon Kim, Jaejin Lee, Hee-Seok Kim, Dong-Hoon Yoo, Sukjin Kim, Hongseok Kim, Soojung Ryu	An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures.	LCTES	2011	DBLP DOI BibTeX RDF
1	D. S. Ivanov	Register allocation with instruction scheduling for VLIW-architectures.	Programming and Computer Software	2010	DBLP DOI BibTeX RDF
1	Sung-Rae Lee, Ser-Hoon Lee, Sun-Young Hwang	A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Dae-Hwan Kim, Hyuk-Jae Lee	Fine-Grain Register Allocation and Instruction Scheduling in a Reference Flow.	Comput. J.	2010	DBLP DOI BibTeX RDF
1	Guillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch	A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures.	ASAP	2010	DBLP DOI BibTeX RDF
1	Masa-Aki Fukase, Ryosuke Murakami, Tomoaki Sato	Design and chip implementation of an instruction scheduling free ubiquitous processor.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Masa-Aki Fukase, Tomoaki Sato	H/S Collaborative Development of a Ubiquitous Processor Free from Instruction Scheduling and Pipeline Disturbance.	ACIS-ICIS	2010	DBLP DOI BibTeX RDF
1	Taniya Siddiqua, Sudhanva Gurumurthi	A multi-level approach to reduce the impact of NBTI on processor functional units.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, NBTI
1	Somnath Paul, Swarup Bhunia	VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.	ISLPED	2010	DBLP DOI BibTeX RDF	narrow-width operand, superscalar processor, within-die variation
1	Tyrel Russell, Abid M. Malik, Michael Chase, Peter van Beek	Learning Heuristics for the Superblock Instruction Scheduling Problem.	IEEE Trans. Knowl. Data Eng.	2009	DBLP DOI BibTeX RDF
1	Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF