| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kieran McLaughlin, Dwayne Burns, Ciaran Toal, Colm McKillen, Sakir Sezer |
Fully hardware based WFQ architecture for high-speed QoS packet scheduling.  |
Integration  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan |
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee |
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Scholze, Holger Eisenreich, Sebastian Höppner, Georg Ellguth, Stephan Henker, Mario Ander, Stefan Hänzsche, Johannes Partzsch, Christian Mayr, René Schüffny |
A 32 GBit/s communication SoC for a waferscale neuromorphic system. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kishor Sarawadekar, Swapna Banerjee |
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenfa Zhan, Aiman El-Maleh |
A new scheme of test data compression based on equal-run-length coding (ERLC). |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Peiravi, Mohammad Asyaei |
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Emmanuel Casseau, Bertrand Le Gal |
Design of multi-mode application-specific cores based on high-level synthesis. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Qian, Yangdong Deng, Bo D. Wang, Shuai Mu |
Towards accelerating irregular EDA applications with GPUs. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitris Bakalis, Haridimos T. Vergos, A. Spyrou |
Efficient modulo 2n±1 squarers. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad |
All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Sun, Joseph R. Cavallaro |
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Özsun S. Sönmez, Günhan Dündar |
Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay |
Low power finite state machine synthesis using power-gating. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Khatir, Alireza Ejlali, Amir Moradi |
Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu |
Capture-power-aware test data compression using selective encoding. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shu-Yi Wong, Chunhong Chen |
Power efficient multi-stage CMOS rectifier design for UHF RFID tags. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Peng Fan, Chia-Hao Fang |
Efficient RC low-power bus encoding methods for crosstalk reduction. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Jin, Yinhe Han, Huawei Li, Xiaowei Li |
Statistical lifetime reliability optimization considering joint effect of process variation and aging. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Keivan Navi, Horialsadat Hossein Sajedi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Ali Jalali, Omid Kavehie |
High-speed full adder based on minority function and bridge style for nanoscale. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | San-Fu Wang, Yuh-Shyan Hwang, Shou-Chung Yan, Jiann-Jong Chen |
A new CMOS wideband low noise amplifier with gain control. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Xu, Gary Gréwal, Shawki Areibi |
StarPlace: A new analytic method for FPGA placement. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lihong Zhang, Zheng Liu |
Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kimmo Järvinen |
Optimized FPGA-based elliptic curve cryptography processor for high-speed applications. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael |
Improved diagnosis using enhanced fault dominance. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristian Ferent, Alex Doboli |
Measuring the uniqueness and variety of analog circuit design features. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andy Rupp, Thomas Eisenbarth, Andrey Bogdanov, Oliver Grieb |
Hardware SLE solvers: Efficient building blocks for cryptographic and cryptanalyticapplications. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner, Abolghasem Zeidaabadi Nezhad |
A nonlinearity error calibration technique for pipelined ADCs. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging reversible circuits. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh |
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massimo Alioto, Gaetano Palumbo, Massimo Poli |
Optimized design of parallel carry-select adders. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kris Gaj, Rainer Steinwandt |
Hardware architectures for algebra, cryptology, and number theory. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo Ye, Qian Zhao, Duo Zhou, Xiaohua Wang, Min Luo |
Test data compression using alternating variable run-length code. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Junfeng Fan, Lejla Batina, Ingrid Verbauwhede |
Design and design methods for unified multiplier and inverter and its application for HECC. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee |
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuo Sakiyama, Miroslav Knezevic, Junfeng Fan, Bart Preneel, Ingrid Verbauwhede |
Tripartite modular multiplication. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Farshidi, Laleh Behjat, Logan M. Rakai, Bahareh Fathi |
A pre-placement individual net length estimation model and an application for modern circuits. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Duo Li, Sheldon X.-D. Tan |
Statistical analysis of large on-chip power grid networks by variational reduction scheme. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles Thangaraj, Alkan Cengiz, Tom Chen |
Rapid design space exploration using legacy design data and technology scaling trend. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou |
Fast modulo 2n+1 multi-operand adders and residue generators. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Ayala, Arvind Sridhar, David Cuesta |
Thermal modeling and analysis of 3D multi-processor chips. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao |
Statistical estimation and evaluation for communication mapping in Network-on-Chip. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Manuel F. M. Barros, Jorge Guilherme, Nuno Horta |
Analog circuits optimization based on evolutionary computation techniques. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bin Zhou, Yizheng Ye, Zhao-lin Li, Jianwei Zhang, Xin-chun Wu, Rui Ke |
A test set embedding approach based on twisted-ring counter with few seeds. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | José M. Granado Criado, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido |
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Wave-pipelined intra-chip signaling for on-FPGA communications. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Achutavarrier Prasad Vinod, Edmund Ming-Kit Lai, Douglas L. Maskell, Pramod Kumar Meher |
An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Kaivani, Ghassem Jaberipur |
Fully redundant decimal addition and subtraction using stored-unibit encoding. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Kabbani |
Logical effort based dynamic power estimation and optimization of static CMOS circuits. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai Liu, Yu Zhou, Yunsong Li, Jian Feng Ma |
A high performance MQ encoder architecture in JPEG2000. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yici Cai, Jin Shi, Shuai Li |
Optimization of via distribution and stacked via in multi-layered P/G networks. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bassel Soudan |
Reducing signal timing variations in inter-core busses. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai |
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajdeep Mukhopadhyay, Anvesh Komuravelli, Pallab Dasgupta, S. K. Panda, Siddhartha Mukhopadhyay |
A static verification approach for architectural integration of mixed-signal integrated circuits. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas |
Low-power current-reused RF front-end based on optimized transformers topology. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie |
Constant addition with flagged binary adder architectures. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiou-Yng Lee |
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m). |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi |
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Manel Puig, José María López-Villegas, Atila Herms |
Erratum to the Special Section on DCIS 2006 [Integration, the VLSI Journal, Volume 42, Issue 3, June 2009]. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xu He, Sheqin Dong, Yuchun Ma |
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Roger Kahn, Shlomo Weiss |
Reducing leakage power with BTB access prediction. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad Patooghy, Seyed Ghassem Miremadi, Mahdi Fazeli |
A low-overhead and reliable switch architecture for Network-on-Chips. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan M. Carrillo, Guido Torelli, Raquel Pérez-Aloe, José M. Valverde, J. Francisco Duque-Carrillo |
Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiying Xue, Tao Li, Yangdong Deng, Zhiping Yu |
Full-chip leakage analysis for 65 nm CMOS technology and beyond. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhi Yang, Guangsheng Ma, Shu Zhang |
Formal verification of high-level data-flow synthesis designs using relational modeling and symbolic computation. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Meysam Zargham, Christian Schlegel, Jorge Pérez Chamorro, Cyril Lahuec, Fabrice Seguin, Michel Jézéquel, Vincent C. Gaudet |
Scaling of analog LDPC decoders in sub-100 nm CMOS processes. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Chen, Takeshi Yoshimura |
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Lech Józwiak, Nadia Nedjah, Miguel Figueroa |
Modern development methods and tools for embedded reconfigurable systems: A survey. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra |
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong |
An MTCMOS technology for low-power physical design. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Fadi Riad Shahroury, Chung-Yu Wu |
A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mariano Jiménez-Fuentes, Ramón González Carvajal, Lucía Acosta, Carlos Rubia-Marcos, Antonio J. López-Martín, Jaime Ramírez-Angulo |
A tunable highly linear CMOS transconductor with 80 dB of SFDR. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Katalin Popovici, Xavier Guerin, Ahmed Amine Jerraya, Kai Huang, Lei Li, Xiaolang Yan |
Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho |
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu |
Handling routability in floorplan design with twin binary trees. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Haixia Yan, Qiang Zhou, Xianlong Hong |
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaizki Mendizabal, Unai Alvarado, I. Guruceaga, Héctor Solar, Andrés Garcia-Alonso, Roc Berenguer |
A dual front-end for the new GPS/GALILEO generation in a 0.35 µm SiGe process. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehie |
A novel low-power full-adder cell for low voltage. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Lars Aspemyr, Henrik Sjöland |
Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeroen De Maeyer, Pieter Rombouts, Ludo Weyten |
Nyquist-criterion based design of a CT SigmaDelta-ADC with a reduced number of comparators. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jarrod A. Roy, Aaron N. Ng, Rajat Aggarwal, Venky Ramachandran, Igor L. Markov |
Solving modern mixed-size placement instances. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ewout Martens, Georges G. E. Gielen |
ANTIGONE: Top-down creation of analog-to-digital converter architectures. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | José M. Solana |
Reducing test application time, test data volume and test power through Virtual Chain Partition. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | David Haley, Vincent C. Gaudet, Chris Winstead, Alex J. Grant, Christian Schlegel |
A dual-function mixed-signal circuit for LDPC encoding/decoding. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Timing analysis with compact variation-aware standard cell models. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | George N. Selimis, Apostolos P. Fournaris, Harris E. Michail, Odysseas G. Koufopavlou |
Improved throughput bit-serial multiplier for GF(2m) fields. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Silvia Franchini, Antonio Gentile, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile |
An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan Antonio Maestro, Pedro Reviriego, Pilar Reyes, Oscar Ruano |
Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ning Mi, Sheldon X.-D. Tan, Boyuan Yan |
Multiple block structure-preserving reduced order modeling of interconnect circuits. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras |
Delay caused by resistive opens in interconnecting lines. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo Liu, Yan Wang, Zhiping Yu, Leibo Liu, Miao Li, Zheng Wang, Jing Lu, Francisco V. Fernández |
Analog circuit optimization system based on hybrid evolutionary algorithms. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi |
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jokin Segundo, Luis Quintanilla, Jesús Arias, Lourdes Enríquez, Jesús M. Hernández-Mangas, José Vicente |
A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rostislav (Reuven) Dobkin, Ran Ginosar |
Two-phase synchronization with sub-cycle latency. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Saurabh Chaudhury, Krishna Teja Sistla, Santanu Chattopadhyay |
Genetic algorithm-based FSM synthesis with area-power trade-offs. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata |
A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny |
QNoC asynchronous router. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Selçuk Talay, Engin Deniz Diktas, Günhan Dündar |
A Sigma-Delta ADC design automation tool with embedded performance estimator. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar S. Elkeelany |
On chip novel video streaming system for bi-network multicasting protocols. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Moradi, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani, Thomas Eisenbarth |
Vulnerability modeling of cryptographic hardware to power analysis attacks. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
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