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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 13 occurrences of 13 keywords
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Rashindra Manniesing, Ireneusz Karkowski, Henk Corporaal |
Automatic SIMD Parallelization of Embedded Applications Based on Pattern Recognition.  |
Euro-Par  |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Maarten Boekhold, Ireneusz Karkowski, Henk Corporaal, Andrea G. M. Cilio |
A Programmable ANSI C Transformation Engine. |
CC |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Maarten Boekhold, Ireneusz Karkowski, Henk Corporaal |
Transformatiing and Parallelizing ANSI C Programs using Pattern Recognition. |
HPCN |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Ireneusz Karkowski, Henk Corporaal |
Exploiting Fine- and Coarse-Grain Parallelism in Embedded Programs. |
IEEE PACT |
1998 |
DBLP DOI BibTeX RDF |
heterogeneous multi-processors, compilers for parallel systems, high performance embedded system design, application-specific architectures |
| 1 | Ireneusz Karkowski, Henk Corporaal |
Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System Design. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
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| 1 | Ireneusz Karkowski, Henk Corporaal |
Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining. |
IEEE PACT |
1997 |
DBLP DOI BibTeX RDF |
heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops |
| 1 | Ireneusz Karkowski, Henk Corporaal |
Overcoming the Limitations of the Traditional Loop Parallelization. |
HPCN |
1997 |
DBLP DOI BibTeX RDF |
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| 1 | Ireneusz Karkowski, Ralph H. J. M. Otten |
Retiming Synchronous Circuitry with Imprecise Delays. |
DAC |
1995 |
DBLP DOI BibTeX RDF |
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| 1 | Ireneusz Karkowski |
Architectural synthesis with possibilistic programming. |
HICSS |
1995 |
DBLP DOI BibTeX RDF |
possibilistic programming, fuzzy mathematical programming, simultaneous scheduling, FOAS, computational complexity, computational complexity, fuzzy logic, high level synthesis, high-level synthesis, circuit CAD, mathematical programming, possibility theory |
Displaying result #1 - #9 of 9 (100 per page; Change: )
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