| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Irith Pomeranz |
Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
On the Computation of Common Test Data for Broadside and Skewed-Load Tests. |
IEEE Trans. Computers |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Fast Identification of Undetectable Transition Faults under Functional Broadside Tests. |
IEEE Trans. Computers |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Undetectable transition faults under broadside tests with constant primary input vectors. |
IET Computers & Digital Techniques |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Test vector chains for increased resolution and reduced storage of diagnostic tests. |
IET Computers & Digital Techniques |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Resolution of Diagnosis Based on Transition Faults. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker |
TSV and DFT cost aware circuit partitioning for 3D-SOCs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. |
J. Low Power Electronics |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Reducing the switching activity of test sequences under transparent-scan. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Scan Shift Power of Functional Broadside Tests. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Generation of Multi-Cycle Broadside Tests. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Primary input cones based on test sequences in synchronous sequential circuits. |
IET Computers & Digital Techniques |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. |
IET Computers & Digital Techniques |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Two-dimensional partially functional broadside tests. |
IET Computers & Digital Techniques |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Sizes of test sets for path delay faults using strong and weak non-robust tests. |
IET Computers & Digital Techniques |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Fixed-State Tests for Delay Faults in Scan Designs. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Broadside and Functional Broadside Tests for Partial-Scan Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On Functional Broadside Tests With Functional Propagation Conditions. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults. |
PRDC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity. |
PRDC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Diagnosis of transition fault clusters. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
Broadside tests, multicycle tests, fault diagnosis, transition faults |
| 1 | J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker |
Fault diagnosis aware ATE assisted test response compaction. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
On clustering of undetectable transition faults in standard-scan circuits. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Built-in generation of functional broadside tests. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker |
Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz |
Max-Fill: A method to generate high quality delay tests. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Test Sequences with Reduced and Increased Switching Activity. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
Diagnostic fault simulation, diagnostic test generation, fault diagnosis, fault collapsing, fault equivalence, fault dominance |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On Test Generation With Test Vector Improvement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
TOV: Sequential Test Generation by Ordering of Test Vectors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On Undetectable Faults and Fault Diagnosis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Static test compaction for diagnostic test sets of full-scan circuits. |
IET Computers & Digital Techniques |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Diagnosis of path delay faults based on low-coverage tests. |
IET Computers & Digital Techniques |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Path Selection for Transition Path Delay Faults. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Switching Activity as a Test Compaction Heuristic for Transition Faults. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz |
Multiple fault activation cycle tests for transistor stuck-open faults. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On Bias in Transition Coverage of Test Sets for Path Delay Faults. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo Yao, Irith Pomeranz, Sudhakar M. Reddy |
Deterministic broadside test generation for transition path delay faults. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
broadside test, deterministic test generation, path delay fault, transition fault |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Input test data volume reduction based on test vector chains. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Functional and partially-functional skewed-load tests. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On multiple bridging faults. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Forming multi-cycle tests for delay faults by concatenating broadside tests. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongok Kim, Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman |
Defect diagnosis based on DFM guidelines. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
interconnect open faults, test generation, bridging faults, static test compaction |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Output-Dependent Diagnostic Test Generation. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
diagnostic test generation, stuck-at faults, full-scan circuits |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On reset based functional broadside tests. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Reducing the storage requirements of a test sequence by using a background vector. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Selecting state variables for improved on-line testability through output response comparison of identical circuits. |
IOLTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits. |
IEEE Trans. Dependable Sec. Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Test vector chains for increasing the fault coverage and numbers of detections. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Definition and generation of partially-functional broadside tests. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Test compaction methods for transition faults under transparent-scan. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Random Test Generation With Input Cube Avoidance. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Fault Diagnosis under Transparent-Scan. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz |
N-distinguishing Tests for Enhanced Defect Diagnosis. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
State persistence: a property for guiding test generation. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
broadside tests, test generation, transition faults, scan-based tests |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Partitioned n-detection test generation. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Definition and application of approximate necessary assignments. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
necessary assignments, random test generation, test generation, stuck-at faults |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. |
European Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Dynamic test compaction for a random test generation procedure with input cube avoidance. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detectability of internal bridging faults in scan chains. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Selection of a fault model for fault diagnosis based on unique responses. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz |
A scalable method for the generation of small test sets. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On-chip Generation of the Second Primary Input Vectors of Broadside Tests. |
DFT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Improving the Detectability of Resistive Open Faults in Scan Cells. |
DFT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. |
DFT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Functional Broadside Tests with Minimum and Maximum Switching Activity. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy |
On Complete Functional Broadside Tests for Transition Faults. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detection of Internal Stuck-open Faults in Scan Chains. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudhakar M. Reddy, Irith Pomeranz, Chen Liu |
On tests to detect via opens in digital CMOS circuits. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
constrained stuck-at tests, test generation, DFT, open defects |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Safe Fault Collapsing Based on Dominance Relations. |
European Test Symposium |
2008 |
DBLP DOI BibTeX RDF |
test generation, bridging faults, fault collapsing, dominance relations |
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Test vector chains for increased targeted and untargeted fault coverage. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
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