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Publications of "Ittetsu Taniguchi" ( http://dblp.L3S.de/Authors/Ittetsu_Taniguchi )

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Publication years (Num. hits)
2006 (1) 2007 (1) 2009 (2) 2010 (2) 2011 (2)
Publication types (Num. hits)
article(2) inproceedings(6)
Venues (Conferences, Journals, ...)
IEICE Transactions(2) ASP-DAC(1) DSD(1) ESTImedia(1) ICPADS(1) ISCAS(1) VLSI-SoC(1)
Authors
Ittetsu Taniguchi(8) Masaharu Imai(5) Yoshinori Takeuchi(5) Keishi Sakanushi(4) Francky Catthoor(3) Praveen Raghavan(3) Ayataka Kobayashi(2) Masahiro Fukui(2) Murali Jayapala(2) Hayato Kanai(1) Hiroaki Takada(1) Hirofumi Kawauchi(1) Hiroyuki Tomiyama(1) Kyoko Ueda(1) Masanori Tsuzuki(1) Midori Sugaya(1) More (+10 of total 19)
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Found 8 publication records. Showing 8 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design. Search on Bibsonomy IEICE Transactions The full citation details ... 2011 DBLP  BibTeX  RDF
1Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating. Search on Bibsonomy DSD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Hirofumi Kawauchi, Masanori Tsuzuki, Ittetsu Taniguchi, Masahiro Fukui An accurate RTL power estimation considering power library unevenness. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai Two-stage configurable decoder model for multiple forward error correction standards. Search on Bibsonomy ESTImedia The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. Search on Bibsonomy IEICE Transactions The full citation details ... 2009 DBLP  BibTeX  RDF
1Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Yutaka Matsubara, Midori Sugaya, Ittetsu Taniguchi, Yasuaki Murakami, Hayato Kanai, Hiroaki Takada SSEST: Summer school on embedded system technologies. Search on Bibsonomy ICPADS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
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